公开(公告)号：US08665601B1

公开(公告)日：2014-03-04

申请号：US12876094

申请日：2010-09-03

Applicant: Rogelio Gazmen Mangay-Ayam, Jr. ,  Elbert Castro Esguerra ,  Jerico Alge Parazo ,  Christopher Dayego Galvez ,  Allan Famitanco Cruz

Inventor： Rogelio Gazmen Mangay-Ayam, Jr. ,  Elbert Castro Esguerra ,  Jerico Alge Parazo ,  Christopher Dayego Galvez ,  Allan Famitanco Cruz

IPC: H05K5/00 ,  H05K1/14 ,  H05K7/00

CPC classification number: G11C5/04 ,  H05K1/144 ,  H05K5/0008 ,  H05K5/0069 ,  H05K7/1417 ,  H05K9/0066 ,  H05K2201/2018

Abstract: The present invention pertains to a hard disk drive form factor compatible solid-state storage device enclosure assembly that protects circuit boards contained within the enclosure from environmental disruption, such as mechanical stress, vibration, external electronic disruption, or any combination of these, while allowing for a variable number of circuit boards in the SSD enclosure. In another embodiment, the solid-state storage device enclosure assembly, or a similar circuit board assembly, includes an alignment guide that precludes a circuit board from being misaligned within the enclosure.

Abstract translation: 本发明涉及一种硬盘驱动器形状因素兼容的固态存储设备外壳组件，其保护包含在外壳内的电路板免受诸如机械应力，振动，外部电子破坏或这些的任何组合之类的环境破坏，同时允许 适用于SSD外壳中可变数量的电路板。 在另一个实施例中，固态存储设备外壳组件或类似的电路板组件包括排除电路板在外壳内不对准的对准引导件。

公开(公告)号：US08447908B2

公开(公告)日：2013-05-21

申请号：US12876247

申请日：2010-09-07

Applicant: Ricardo H. Bruce ,  Elsbeth Lauren T. Villapana ,  Joel A. Baylon

Inventor： Ricardo H. Bruce ,  Elsbeth Lauren T. Villapana ,  Joel A. Baylon

IPC: G06F13/28 ,  G06F13/36 ,  G06F9/44

CPC classification number: G06F13/1657 ,  G06F12/00 ,  G06F12/0246 ,  G06F13/1673 ,  G06F13/1684 ,  G06F13/36

Abstract: The present invention relates to a multilevel memory bus system for transferring information between at least one DMA controller and at least one solid-state semiconductor memory device, such as NAND flash memory devices or the like. This multilevel memory bus system includes at least one DMA controller coupled to an intermediate bus; a flash memory bus; and a flash buffer circuit between the intermediate bus and the flash memory bus. This multilevel memory bus system may be disposed to support: an n-bit wide bus width, such as nibble-wide or byte-wide bus widths; a selectable data sampling rate, such as a single or double sampling rate, on the intermediate bus; a configurable bus data rate, such as a single, double, quad, or octal data sampling rate; CRC protection; an exclusive busy mechanism; dedicated busy lines; or any combination of these.

Abstract translation: 本发明涉及用于在至少一个DMA控制器与至少一个固态半导体存储器件（诸如NAND闪存器件等）之间传送信息的多电平存储器总线系统。 该多电平存储器总线系统包括耦合到中间总线的至少一个DMA控制器; 闪存总线; 以及中间总线和闪存总线之间的闪存缓冲电路。 该多级存储器总线系统可以被设置为支持：n位宽的总线宽度，例如半字节宽度或字节宽度的总线宽度; 中间总线上的可选择的数据采样率，例如单次或双次采样率; 可配置的总线数据速率，例如单，双，四进制或八进制数据采样率; CRC保护; 独家繁忙的机制; 专线忙 或这些的任何组合。

公开(公告)号：US08165301B1

公开(公告)日：2012-04-24

申请号：US11398321

申请日：2006-04-04

Applicant: Rey Bruce ,  Marizonne Operio Fuentes ,  Raquel Bautista David

Inventor： Rey Bruce ,  Marizonne Operio Fuentes ,  Raquel Bautista David

IPC: H04L9/06

CPC classification number: H04L9/0894 ,  G06F21/82 ,  H04L9/0822

Abstract: A protocol for providing secured IO device and storage controller handshake protocol; IO device controlled cipher settings, and secured data storage and access in memory. An IO device requesting data transfer with encryption and/or decryption, requests session keys from the processor. The processor generates a fresh public-private key pair for the session. The public key is sent to the requesting IO device; the private key is momentarily saved by the processor for the session. The requesting IO device generates a secret key and its desired cipher setting; furthermore, encrypts the secret key and cipher setting using the public key, and sends secret key and cipher setting to the processor. The processor uses the private key to decrypt the secret key and cipher setting. The cipher setting is used for configuring the data processing core. The secret key is used for encryption and/or decryption of the data being transferred. All keys are not permanently saved.

Abstract translation: 用于提供安全的IO设备和存储控制器握手协议的协议; IO设备控制密码设置，以及安全的数据存储和内存访问。 通过加密和/或解密请求数据传输的IO设备从处理器请求会话密钥。 处理器为会话生成一个新的公私密钥对。 公钥被发送到请求的IO设备; 私钥由处理器暂时保存用于会话。 请求的IO设备生成秘密密钥及其期望的密码设置; 此外，使用公钥加密秘密密钥和密码设置，并向处理器发送秘密密钥和密码设置。 处理器使用私钥来解密密钥和密码设置。 密码设置用于配置数据处理核心。 秘密密钥用于对正在传送的数据进行加密和/或解密。 所有键都不会永久保存。

公开(公告)号：US08093103B2

公开(公告)日：2012-01-10

申请号：US12907023

申请日：2010-10-18

Applicant: Rey H. Bruce ,  Ricardo H. Bruce ,  Patrick Digamon Bugayong ,  Joel Alonzo Baylon

Inventor： Rey H. Bruce ,  Ricardo H. Bruce ,  Patrick Digamon Bugayong ,  Joel Alonzo Baylon

IPC: G01R31/26 ,  H01L21/66 ,  H01L21/50 ,  H01L21/48 ,  H01L21/44

CPC classification number: H01L25/105 ,  H01L24/16 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/16 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01079 ,  H01L2924/15331 ,  H01L2924/1627

Abstract: Stacking techniques are illustrated in example embodiments of the present invention wherein semiconductor dies are mounted in a module to become a MCM which serves as the basic building block. A combination of these modules and dies in a substrate creates a package with specific function or a range of memory capacity. Several example system configurations are provided using BGA and PGA to illustrate the stacking technique. Several pin assignment and signal routing techniques are illustrated wherein internal and external signals are routed from main board to various stacked modules. Expansion can be done both on the vertical and horizontal orientations.

Abstract translation: 堆叠技术在本发明的示例性实施例中示出，其中将半导体管芯安装在模块中以成为用作基本构建块的MCM。 衬底中的这些模块和管芯的组合产生具有特定功能或一系列存储器容量的封装。 使用BGA和PGA提供了几个示例系统配置来说明堆叠技术。 示出了几个引脚分配和信号路由技术，其中内部和外部信号从主板路由到各种堆叠的模块。 可以在垂直和水平方向进行扩展。

公开(公告)号：US20100095053A1

公开(公告)日：2010-04-15

申请号：US12575480

申请日：2009-10-08

Applicant: Rey H. BRUCE ,  Noeme P. Mateo ,  Ricky S. Nite

Inventor： Rey H. BRUCE ,  Noeme P. Mateo ,  Ricky S. Nite

IPC: G06F12/00 ,  G06F12/02 ,  G06F13/28

CPC classification number: G06F13/28 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0685 ,  G06F12/0866 ,  G06F12/0897 ,  G06F2212/2022 ,  G06F2212/217

Abstract: A hybrid storage system comprising mechanical disk drive means, flash memory means, SDRAM memory means, and SRAM memory means is described. IO processor means and DMA controller means are devised to eliminate host intervention. Multi-tiered caching system and novel data structure for mapping logical address to physical address results in a configurable and scalable high performance computer data storage solution.

Abstract translation: 描述了包括机械盘驱动装置，闪存装置，SDRAM存储装置和SRAM存储装置的混合存储系统。 IO处理器装置和DMA控制器装置被设计为消除主机干预。 多层缓存系统和用于将逻辑地址映射到物理地址的新颖数据结构导致可配置和可扩展的高性能计算机数据存储解决方案。

公开(公告)号：US07620748B1

公开(公告)日：2009-11-17

申请号：US11399736

申请日：2006-04-06

Applicant: Ricardo Bruce ,  Rey Bruce ,  Federico Zalzos Sambilay, Jr. ,  Bernard Sherwin Leung Chiw

Inventor： Ricardo Bruce ,  Rey Bruce ,  Federico Zalzos Sambilay, Jr. ,  Bernard Sherwin Leung Chiw

IPC: G06F13/28 ,  G06F13/36

CPC classification number: G06F13/28

Abstract: In conventional storage device system, data transfer from memory to IO bus has to go through an intermediate volatile memory (cache). Data transfer therefore is completed in two steps—data is transferred from memory to cache and then from cache to the IO bus. Memory-to-cache transfer is handled by one DMA engine and another DMA engine for cache-to-IO transfer. To start the transfer, processor prepares the DMA transfer from memory to cache. Upon completion of the memory-to-cache transfer, the processor is interrupted to prepare the transfer from cache to IO. In between transfers, the processor has to intervene to setup the next transfer utilizing the precious processor cycles. The present invention improves on the above process using two novel schemes; 1) The use of dependency table to facilitate the transfer from memory-to-IO with less intervention from the processor and 2) the use of Bus Snooping scheme to bypass the transfer to cache making the transfer directly from memory to IO bus. This makes the transfer from memory to IO completed in single transfer.

Abstract translation: 在传统的存储设备系统中，从存储器到IO总线的数据传输必须经过中间的易失性存储器（cache）。 因此，数据传输在两个步骤中完成 - 数据从存储器传输到缓存，然后从缓存传输到IO总线。 内存到高速缓存传输由一个DMA引擎和另一个DMA引擎来处理，用于缓存到IO传输。 为了开始传输，处理器准备从存储器到缓存的DMA传输。 在内存到高速缓存传输完成后，处理器被中断以准备从缓存到IO的传输。 在传输之间，处理器必须介入以利用宝贵的处理器周期设置下一个传输。 本发明使用两种新颖的方案改进了上述过程; 1）使用依赖关系表，以便从处理器的干预更少，从内存到IO的传输，以及2）使用总线侦听方案绕过传输缓存，从而将传输直接从内存传输到IO总线。 这使得从内存到IO的传输在单次传输中完成。

公开(公告)号：US07506098B2

公开(公告)日：2009-03-17

申请号：US11450005

申请日：2006-06-08

Applicant: Mark Arcedera ,  Reyjan C. Lanuza ,  Ritchie Babaylan

Inventor： Mark Arcedera ,  Reyjan C. Lanuza ,  Ritchie Babaylan

IPC: G06F12/00

CPC classification number: G06F12/0246

Abstract: A data storage system is provided comprising several flash arrays in a board and stacking these boards to attain a high-capacity solid state hard drive. A remap table is used to map all logical addresses from a host system to the actual physical addresses where data are stored. The assignments of these physical locations are done in such a way that the load of the system is evenly distributed to its available resources. This would ensure that the storage system will run at its utmost efficiency utilizing its resources properly. To achieve this, the system would make sure that the physical location of data be evenly distributed according to the current load of the system.

Abstract translation: 提供一种数据存储系统，其包括板中的几个闪存阵列并且堆叠这些板以获得高容量固态硬盘驱动器。 重映射表用于将来自主机系统的所有逻辑地址映射到存储数据的实际物理地址。 这些物理位置的分配以使系统的负载均匀分布到其可用资源的方式完成。 这将确保存储系统以最佳效率利用其资源正常运行。 为了实现这一点，系统将确保数据的物理位置根据系统的当前负载均匀分布。

公开(公告)号：US10055150B1

公开(公告)日：2018-08-21

申请号：US15170768

申请日：2016-06-01

Applicant: BiTMICRO Networks, Inc.

Inventor： Marvin Dela Cruz Fenol ,  Jik-Jik Oyong Abad ,  Precious Nezaiah Umali Pestano

IPC: G06F3/06 ,  G06F12/0804 ,  G06F12/121

CPC classification number: G06F12/121 ,  G06F12/0804 ,  G06F12/0868 ,  G06F2212/1041 ,  G06F2212/222

Abstract: In an embodiment of the invention, a method comprises: requesting an update on a control data in at least one flash block in a storage memory; replicating, from the storage memory to a cache memory, the control data to be updated; moving a clean cache link list to a dirty cache link list so that the dirty cache link list is changed to reflect the update on the control data; and moving the dirty cache link list to a for-flush link list and writing an updated control data from the for-flush link list to a free flash page in the storage memory. In another embodiment of the invention, an apparatus comprises: a control data flushing system configured to: request an update on a control data in at least one flash block in a storage memory; replicate, from the storage memory to a cache memory, the control data to be updated; move a clean cache link list to a dirty cache link list so that the dirty cache link list is changed to reflect the update on the control data; and move the dirty cache link list to a for-flush link list and write an updated control data from the for-flush link list to a free flash page in the storage memory. In yet another embodiment of the invention, an article of manufacture, comprises a non-transient computer-readable medium having stored thereon instructions operable to permit an apparatus to: request an update on a control data in at least one flash block in a storage memory; replicate, from the storage memory to a cache memory, the control data to be updated; move a clean cache link list to a dirty cache link list so that the dirty cache link list is changed to reflect the update on the control data; and move the dirty cache link list to a for-flush link list and write an updated control data from the for-flush link list to a free flash page in the storage memory.

公开(公告)号：US10042792B1

公开(公告)日：2018-08-07

申请号：US14688748

申请日：2015-04-16

Applicant: BiTMICRO Networks, Inc.

Inventor： Amor Leo Saing Ricaborda ,  Alain Vincent Villaranda Abitria ,  Rose Fay M. Orcullo

IPC: G06F13/20 ,  G06F13/28 ,  G06F13/42 ,  G06F12/02

CPC classification number: G06F13/28 ,  G06F12/0246 ,  G06F13/4221 ,  G06F13/4295 ,  G06F2212/7201 ,  G06F2213/0026

Abstract: In an embodiment of the invention, a method comprises: transmitting, by a host side, an exchange message protocol (EMP) command frame to a memory device side; informing, by the host side, the memory device side to process the command frame; executing, by the memory device side, the command frame; and transmitting, by the memory device side, an EMP response frame to the host side, in response to the command frame. In another embodiment of the invention, an apparatus comprises: a host side configured to transmit an exchange message protocol (EMP) command frame to a memory device side; wherein the host side is configured to inform the memory device side to process the command frame; wherein the memory device side is configured to execute the command frame; and wherein the memory device side is configured to transmit an EMP response frame to the host side, in response to the command frame.

公开(公告)号：US10007561B1

公开(公告)日：2018-06-26

申请号：US15483893

申请日：2017-04-10

Applicant: BiTMICRO Networks, Inc.

Inventor： Bharadwaj Pudipeddi ,  Jeffrey Bunting ,  Lihan Chang

IPC: G06F9/46 ,  G06F9/50

CPC classification number: G06F9/5083 ,  G06F9/5061

Abstract: The invention is an apparatus for dynamic provisioning available as a multi-mode device that can be dynamically configured for balancing between storage performance and hardware acceleration resources on reconfigurable hardware such as an FPGA. An embodiment of the invention provides a cluster of these multi-mode devices that form a group of resilient Storage and Acceleration elements without requiring a dedicated standby storage spare. Yet another embodiment of the invention provides an interconnection network attached cluster configured to dynamically provision full acceleration and storage resources to meet an application's needs and end-of-life requirements of an SSD.