公开(公告)号：US08123963B2

公开(公告)日：2012-02-28

申请号：US12152241

申请日：2008-05-12

Applicant: Hubert Benzel ,  Heribert Weber ,  Hans Artmann ,  Frank Schaefer

Inventor： Hubert Benzel ,  Heribert Weber ,  Hans Artmann ,  Frank Schaefer

IPC: H01L21/302 ,  B81C1/00

CPC classification number: G01L9/0042 ,  B81B2201/0264 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C1/00047 ,  B81C1/00595 ,  B81C2201/0115 ,  G01L9/0045 ,  H01L21/3063

Abstract: A method for producing a semiconductor component includes forming an n-doped layer in a p-doped layer of the semiconductor component, wherein the n-doped layer comprises at least one of: a sieve-like layer or a network-like layer. The method also includes porously etching the p-doped layer between the material of the n-doped layer to form a top electrode, and forming a cavity below the n-doped layer.

Abstract translation: 一种制造半导体部件的方法包括在所述半导体部件的p掺杂层中形成n掺杂层，其中所述n掺杂层包括以下中的至少一种：筛状层或网状层。 该方法还包括在n掺杂层的材料之间对p-掺杂层进行腐蚀蚀刻以形成顶部电极，以及在n-掺杂层下方形成空腔。

公开(公告)号：US07892440B1

公开(公告)日：2011-02-22

申请号：US11828639

申请日：2007-07-26

Applicant: Shekhar Bhansali ,  Abdur Rub Abdur Rahman ,  Sunny Kedia

Inventor： Shekhar Bhansali ,  Abdur Rub Abdur Rahman ,  Sunny Kedia

IPC: B44C1/22

CPC classification number: B81C1/005 ,  B81B2203/0353 ,  B81C1/00619 ,  B81C2201/0115 ,  B81C2201/0133 ,  B81C2201/0136 ,  H01L21/02052 ,  H01L21/3063

Abstract: The present invention illustrates a bulk silicon etching technique that yields straight sidewalls, through wafer structures in very short times using standard silicon wet etching techniques. The method of the present invention employs selective porous silicon formation and dissolution to create high aspect ratio structures with straight sidewalls for through wafer MEMS processing.

Abstract translation: 本发明示出了使用标准硅湿式蚀刻技术在非常短的时间内通过晶片结构产生直的侧壁的体硅蚀刻技术。 本发明的方法采用选择性多孔硅形成和溶解以产生具有用于晶片MEMS加工的直侧壁的高纵横比结构。

公开(公告)号：US20100003790A1

公开(公告)日：2010-01-07

申请号：US12305150

申请日：2007-08-21

Applicant: Silvia Kronmueller ,  Tino Fuchs ,  Ando Feyh ,  Christina Leinenbach ,  Marco Lammer

Inventor： Silvia Kronmueller ,  Tino Fuchs ,  Ando Feyh ,  Christina Leinenbach ,  Marco Lammer

IPC: H01L21/50

CPC classification number: B81C1/00333 ,  B81C2201/0115 ,  B81C2201/0132 ,  B81C2203/0136 ,  B81C2203/0145

Abstract: A capping technology is provided in which, despite the fact that structures which are surrounded by a silicon-germanium filling layer are exposed using ClF3 etching through micropores in the silicon cap, an etching attack on the silicon cap is prevented, namely, either by particularly selective (approximately 10,000:1 or higher) adjustment of the etching process itself, or by using the finding that the oxide of a germanium-rich layer, in contrast to oxidized porous silicon, is not stable but instead may be easily dissolved, to protect the silicon cap.

Abstract translation: 提供了一种封盖技术，尽管事实上，利用ClF3蚀刻通过硅盖中的微孔暴露由硅 - 锗填充层包围的结构，但是防止了对硅帽的蚀刻攻击，即特别地 选择性（大约10,000:1或更高）调整蚀刻工艺本身，或通过使用与氧化多孔硅相反的富锗层的氧化物不稳定但可以容易地溶解的发现来保护 硅帽。

公开(公告)号：US07479234B2

公开(公告)日：2009-01-20

申请号：US10492009

申请日：2002-09-04

Applicant: Hubert Benzel ,  Heribert Weber ,  Frank Schaefer

Inventor： Hubert Benzel ,  Heribert Weber ,  Frank Schaefer

IPC: H01B13/00

CPC classification number: B81C1/00047 ,  B81C1/00246 ,  B81C2201/0115 ,  B81C2201/014

Abstract: A method is proposed which will enable cavities having optically transparent walls to be produced simply and cost-effectively in a component by using standard methods of microsystems technology. For this purpose, a silicon region is first produced, which is surrounded on all sides by at least one optically transparent cladding layer. At least one opening is then produced in the cladding layer. Over this opening, the silicon surrounded by the cladding layer is dissolved out, forming a cavity within the cladding layer. In this context, the cladding layer acts as an etch barrier layer.

Abstract translation: 提出了一种通过使用微系统技术的标准方法，能够简单且成本有效地在部件中产生具有光学透明壁的空腔的方法。 为此目的，首先制造出硅区域，其通过至少一个光学透明覆层在所有侧面上被包围。 然后在包层中产生至少一个开口。 在该开口上，由包覆层包围的硅被溶出，在包覆层内形成空腔。 在本文中，包覆层用作蚀刻阻挡层。

公开(公告)号：US07456112B2

公开(公告)日：2008-11-25

申请号：US11327463

申请日：2006-01-09

Applicant: Chang-seung Lee

Inventor： Chang-seung Lee

IPC: H01L21/302

CPC classification number: B81C1/00111 ,  A61M37/0015 ,  A61M2037/0053 ,  B81B2201/055 ,  B81C2201/0115

Abstract: A method of fabricating a micro-needle array is provided. The method of fabricating a micro-needle array having a substrate having a first surface and a second surface spaced in a predetermined interval apart from the first surface, includes patterning on the first surface, thereby forming a shape of micro-needle bodies. Further, micro-passageways are formed that penetrate the first surface of the substrate from the second surface by a porous silicon process, and integrates the micro-passageways, thereby forming the bodies and channels of micro-needles.

Abstract translation: 提供一种制造微针阵列的方法。 制造具有第一表面和与第一表面隔开预定间隔的第二表面的基底的微针阵列的方法包括在第一表面上的图案化，从而形成微针体的形状。 此外，通过多孔硅工艺形成从第二表面穿透基板的第一表面的微通道，并且将微通道整合，从而形成微针的主体和通道。

公开(公告)号：US07433811B2

公开(公告)日：2008-10-07

申请号：US10838859

申请日：2004-05-04

Applicant: Jun Gao ,  Michael J. Sailor ,  Sangeeta Bhatia ,  Christopher Flaim

Inventor： Jun Gao ,  Michael J. Sailor ,  Sangeeta Bhatia ,  Christopher Flaim

IPC: G06F17/50 ,  C23C20/00

CPC classification number: B81C1/00515 ,  B81C2201/0114 ,  B81C2201/0115 ,  C25F3/12 ,  C25F3/14 ,  H01L21/3063

Abstract: The invention is directed to methods for direct patterning of silicon. The invention provides the ability to fabricate complex surfaces in silicon with three dimensional features of high resolution and complex detail. The invention is suitable, for example, for use in soft lithography as embodiments of the invention can quickly create a master for use in soft lithography. In an embodiment of the invention, electrochemical etching of silicon, such as a silicon wafer, for example, is conducted while at least a portion of the silicon surface is exposed to an optical pattern. The etching creates porous silicon in the substrate, and removal of the porous silicon layer leaves a three-dimensional structure correlating to the optical pattern.

Abstract translation: 本发明涉及直接图案化硅的方法。 本发明提供了在硅中制造具有高分辨率和复杂细节的三维特征的复杂表面的能力。 本发明适用于例如在软光刻中使用，因为本发明的实施例可以快速地创建用于软光刻的母版。 在本发明的一个实施例中，例如硅的电化学蚀刻被进行，同时硅表面的至少一部分暴露于光学图案。 蚀刻在衬底中产生多孔硅，并且去除多孔硅层留下与光学图案相关的三维结构。

公开(公告)号：US20080197106A1

公开(公告)日：2008-08-21

申请号：US12011711

申请日：2008-01-28

Applicant: Ando Feyh

Inventor： Ando Feyh

IPC: C23F17/00 ,  A61M5/00

CPC classification number: B81C1/00111 ,  B81B2201/055 ,  B81C2201/0115

Abstract: A method for manufacturing semiconical microneedles in an Si-semiconductor substrate and a semiconical microneedles manufacturable made by this method.

Abstract translation: 在半导体硅衬底制造半导体微针的方法和通过该方法制造的半导体微针。

公开(公告)号：US20080093694A1

公开(公告)日：2008-04-24

申请号：US12001289

申请日：2007-12-10

Applicant: Hubert Benzel ,  Heribert Weber ,  Hans Artmann ,  Thorsten Pannek ,  Frank Schafer

Inventor： Hubert Benzel ,  Heribert Weber ,  Hans Artmann ,  Thorsten Pannek ,  Frank Schafer

IPC: H01L29/02 ,  H01L21/02

CPC classification number: B81C1/00182 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/0115 ,  B81C2201/0136 ,  G01L9/0042

Abstract: In a method for manufacturing a semiconductor component having a semiconductor substrate, a flat, porous diaphragm layer and a cavity underneath the porous diaphragm layer are produced to form unsupported structures for a component. In a first approach, the semiconductor substrate may receive a doping in the diaphragm region that is different from that of the cavity. This permits different pore sizes and/or porosities to be produced, which is used in producing the cavity for improved etching gas transport. Also, mesopores may be produced in the diaphragm region and nanopores may be produced as an auxiliary structure in what is to become the cavity region.

Abstract translation: 在制造具有半导体衬底的半导体部件的方法中，制造平坦的多孔隔膜层和多孔隔膜层下方的空腔，以形成用于部件的无支撑结构。 在第一种方法中，半导体衬底可以在膜片区域中接收不同于空腔的掺杂。 这允许产生不同的孔径和/或孔隙率，其用于制造用于改善蚀刻气体输送的空腔。 此外，可以在隔膜区域中产生中孔，并且可以在将要成为空腔区域的地方制造纳米孔作为辅助结构。

公开(公告)号：US20070298532A1

公开(公告)日：2007-12-27

申请号：US11476392

申请日：2006-06-27

Applicant: Andrew Machauf

Inventor： Andrew Machauf

IPC: H01L21/00

CPC classification number: B81C1/00333 ,  B81C2201/0115 ,  B81C2203/0136 ,  B81C2203/0145 ,  B81C2203/019

Abstract: An apparatus comprising a substrate having therein one or more porous regions, a micro-electro-mechanical (MEMS) device formed on the substrate, a cap formed on the substrate, wherein the cap encapsulates the MEMS device and is formed over at least one of the one or more porous regions, and a sealing layer formed on a back side of the substrate. A process comprising forming one or more porous regions in a substrate, forming a micro-electro-mechanical (MEMS) device on the substrate, forming a sacrificial layer on the substrate over the MEMS device, wherein the sacrificial layer is over at least one of the one or more porous regions, forming a cap on the substrate, wherein the cap encapsulates the MEMS device and the sacrificial layer, etching the sacrificial layer inside the cap by inserting etchant through at least one of the one or more porous regions, and forming a sealing layer on a back side of the substrate.

Abstract translation: 一种包括其中具有一个或多个多孔区域的基板的装置，形成在所述基板上的微机电（MEMS）装置，形成在所述基板上的盖，其中所述盖封装所述MEMS装置，并且形成在所述基板上的至少一个上 所述一个或多个多孔区域和形成在所述基板的背面上的密封层。 一种方法，包括在衬底中形成一个或多个多孔区域，在衬底上形成微电子机械（MEMS）器件，在MEMS器件上在衬底上形成牺牲层，其中牺牲层在 所述一个或多个多孔区域在所述衬底上形成帽，其中所述帽封装所述MEMS器件和所述牺牲层，通过将所述一个或多个多孔区域中的至少一个插入蚀刻剂来蚀刻所述帽内的所述牺牲层，以及形成 在基板的背面上的密封层。

公开(公告)号：US07306966B2

公开(公告)日：2007-12-11

申请号：US10486182

申请日：2002-07-25

Applicant: Hubert Benzel ,  Heribert Weber ,  Hans Artmann ,  Thorsten Pannek ,  Frank Schäfer

Inventor： Hubert Benzel ,  Heribert Weber ,  Hans Artmann ,  Thorsten Pannek ,  Frank Schäfer

IPC: H01L21/00

CPC classification number: B81C1/00182 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C2201/0115 ,  B81C2201/0136 ,  G01L9/0042

Abstract: In a method for manufacturing a semiconductor component having a semiconductor substrate, a flat, porous diaphragm layer and a cavity underneath the porous diaphragm layer are produced to form unsupported structures for a component. In a first approach, the semiconductor substrate may receive a doping in the diaphragm region that is different from that of the cavity. This permits different pore sizes and/or porosities to be produced, which is used in producing the cavity for improved etching gas transport. Also, mesopores may be produced in the diaphragm region and nanopores may be produced as an auxiliary structure in what is to become the cavity region.

Abstract translation: 在制造具有半导体衬底的半导体部件的方法中，制造平坦的多孔隔膜层和多孔隔膜层下方的空腔，以形成用于部件的无支撑结构。 在第一种方法中，半导体衬底可以在膜片区域中接收不同于空腔的掺杂。 这允许产生不同的孔径和/或孔隙率，其用于制造用于改善蚀刻气体输送的空腔。 此外，可以在隔膜区域中产生介孔，并且可以在将要成为空腔区域的地方制造纳米孔作为辅助结构。