公开(公告)号：US06759863B2

公开(公告)日：2004-07-06

申请号：US09854905

申请日：2001-05-15

申请人： Brian Moore

发明人： Brian Moore

IPC分类号： G01R3102

CPC分类号： G01R31/2884 ,  G01R31/2831 ,  G01R31/3025 ,  G01R31/303 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： The present invention is for an apparatus and method for the wireless testing of Integrated Circuits and wafers. The apparatus comprises a test unit external from the wafer and at least one test circuit which is fabricated on the wafer which contains the Integrated Circuit. The test unit transmits an RF signal to power the test circuit. The test circuit, comprising a variable ring oscillator, performs a series of parametric tests at the normal operating frequency of the Integrated Circuit and transmits the test results to the test unit for analysis.

摘要翻译： 本发明是用于集成电路和晶片的无线测试的装置和方法。 该装置包括从晶片外部的测试单元和在包含集成电路的晶片上制造的至少一个测试电路。 测试单元发送RF信号为测试电路供电。 包括可变环形振荡器的测试电路在集成电路的正常工作频率下执行一系列参数测试，并将测试结果发送到测试单元进行分析。

公开(公告)号：US06603316B2

公开(公告)日：2003-08-05

申请号：US09905922

申请日：2001-07-17

申请人： Hideo Oishi

发明人： Hideo Oishi

IPC分类号： H01H3112

CPC分类号： G01R31/2879 ,  G01R31/2831 ,  G01R31/30 ,  G01R31/303

摘要： A semiconductor wafer test system for carrying out a burn-in test on a semiconductor wafer including multiple semiconductor devices thereon. A metal interconnect is connected to the gate electrode of each of those devices. A power supply applies an ac voltage of predetermined amplitude to a conductive plate, which creates an ac electric field to be placed on the devices. The ac field should have an intensity at least equal to a minimum value required for the burn-in test and less than a critical value, below which no breakdown occurs in the gate oxide film of each device. By changing the amount of time for which the devices are exposed to the ac field, the burn-in period can be changed freely. In addition, forward and reverse fields are both placed on the gate oxide film of each device. Thus, failures can be screened out very effectively.

公开(公告)号：US20030129776A1

公开(公告)日：2003-07-10

申请号：US10338832

申请日：2003-01-09

发明人： Tae-min Eom ,  Chung-sam Jun ,  Yu-sin Yang

IPC分类号： H01L021/66 ,  G01R031/26 ,  H01L021/44

CPC分类号： H01L22/12 ,  G01R31/303 ,  H01L21/76802 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of monitoring contact holes of an integrated circuit using corona charges is provided for determining whether the contact holes are open. The method includes transmitting corona charges over a unit chip having contact holes on a semiconductor wafer; measuring the surface voltage of the unit chip; making a graph illustrating a relationship between the amount of corona charges transmitted and the measured surface voltage of the unit chip; and analyzing the graph to determine whether the contact holes of the unit chip are open. According to the method of the present invention, contact holes may be monitored at an in-line state when manufacturing an integrated circuit by transmitting corona charges onto a unit chip, eliminating the need to use a scanning electronic microscope, thereby preventing a reduction in yield.

摘要翻译： 提供了使用电晕电荷监测集成电路的接触孔的方法，用于确定接触孔是否打开。 该方法包括在半导体晶片上具有接触孔的单元芯片上传送电晕电荷; 测量单元芯片的表面电压; 示出了发射的电晕电荷量与单位芯片的测量的表面电压之间的关系的曲线图; 并分析图形以确定单元芯片的接触孔是否打开。 根据本发明的方法，当通过将电晕电荷传输到单元芯片上制造集成电路时，可以以在线状态监视接触孔，从而不需要使用扫描电子显微镜，从而防止产量降低 。

公开(公告)号：US06496013B1

公开(公告)日：2002-12-17

申请号：US09509250

申请日：2000-03-23

申请人： Manfred Buks ,  Karim Hosseini

发明人： Manfred Buks ,  Karim Hosseini

IPC分类号： H01H3104

CPC分类号： G01R31/302 ,  G01R29/0878 ,  G01R31/303 ,  G01R31/304

摘要： An instrument to test electronic components, the instrument including a drive unit electrically connecting the component and electrically driving the component to generate a field in the nearby space. The instrument also includes a test device electrically insulated from the component and mounted in its vicinity in order to measure the field generated by the component. The drive unit is designed to apply a voltage to the component. The test device includes an instrument amplifier measuring the voltage differential of two electrodes positioned at two sites in the electric field generated by the component. One of the electrodes is positioned near the component.

摘要翻译： 一种用于测试电子部件的仪器，所述仪器包括电连接所述部件并电驱动所述部件以在附近空间中产生场的驱动单元。 该仪器还包括与部件电绝缘并安装在其附近的测试装置，以便测量由部件产生的磁场。 驱动单元设计用于向组件施加电压。 测试装置包括一个仪器放大器，用于测量位于由该部件产生的电场中的两个位置处的两个电极的电压差。 电极中的一个位于组件附近。

公开(公告)号：US06448096B1

公开(公告)日：2002-09-10

申请号：US09864656

申请日：2001-05-23

申请人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

发明人： Jeffrey D. Birdsley ,  Michael R. Bruce ,  Brennan V. Davis ,  Rosalinda M. Ring ,  Daniel L. Stone

IPC分类号： H01L2100

CPC分类号： G01Q60/30 ,  G01R31/303 ,  Y10S977/854

摘要： Analysis of a semiconductor die having silicon-on-insulator (SOI) structure is enhanced by accessing the circuitry within the die from the back side without necessarily breaching the insulator layer of the SOI structure. According to an example embodiment of the present invention, a semiconductor die having a SOI structure and a backside opposite circuitry in a circuit side is analyzed. An atomic force microscope is scanned across a thinned portion of the back side. The microscope responds to an electrical characteristic, such as a logic state, coupled from circuitry via the insulator portion of the die over which the microscope is being scanned. The response of the microscope to the die is detected and used to detect an electrical characteristic of the die.

摘要翻译： 通过从背面访问管芯内的电路而不必破坏SOI结构的绝缘体层来增强具有绝缘体上硅（SOI）结构的半导体管芯的分析。 根据本发明的示例性实施例，分析了具有SOI结构的半导体管芯和电路侧的背面相反的电路。 原子力显微镜扫描在背面的薄部分。 显微镜响应诸如逻辑状态的电特性，该电特性通过显微镜正被扫描的裸片的绝缘体部分从电路耦合。 检测显微镜对管芯的响应，并用于检测管芯的电气特性。

公开(公告)号：US20020058343A1

公开(公告)日：2002-05-16

申请号：US09865265

申请日：2001-05-25

发明人： Alexei Gruverman ,  Masahiro Tanaka

IPC分类号： H01L021/00

CPC分类号： G01R31/27 ,  G01R31/028 ,  G01R31/2648 ,  G01R31/303 ,  H01L28/55

摘要： A method is provided for evaluating a ferroelectric capacitor by examining a structure in a prescribed area on a surface of a ferroelectric membrane using a piezo-response mode of a scanning force microscope. The method adopts a layered structure, in which an electrode and the ferroelectric membrane form a pseudo ohmic contact, and comprises the steps of: inducing a localized polarization inversion in a selected crystal grain in the ferroelectric membrane by imposing a voltage pulse having a prescribed polarity; determining a retention time by obtaining a piezo-response image for a prescribed time till a complete inversion of a write domain; and determining a retention characteristic by measuring a time till a complete disappearance of a switched domain or by measuring a time-dependency at a region where the polarization inversion are being retained.

摘要翻译： 提供了一种通过使用扫描力显微镜的压电响应模式检查铁电体膜表面上的规定区域中的结构来评估铁电电容器的方法。 该方法采用层状结构，其中电极和铁电膜形成伪欧姆接触，并且包括以下步骤：通过施加具有规定极性的电压脉冲，在铁电膜中选择的晶粒中引起局部极化反转 ; 通过获得压缩响应图像达预定时间直到写入域的完全反转来确定保持时间; 以及通过测量开关域完全消失之前的时间或通过测量在保持极化反转的区域的时间依赖性来确定保持特性。

公开(公告)号：US06294396B1

公开(公告)日：2001-09-25

申请号：US09461512

申请日：1999-12-14

申请人： Takeshi Nogami ,  Susan Chen ,  Imran Hashim

发明人： Takeshi Nogami ,  Susan Chen ,  Imran Hashim

IPC分类号： H01L2166

CPC分类号： G01R31/303 ,  G01R31/307 ,  G01R31/311

摘要： The barrier effectiveness of a barrier material with respect to a conductive material is evaluated by providing a silicon substrate and then etching said silicon substrate to define an opening therein. The barrier material is then deposited in the opening, followed by a deposition of the conductive material. The silicon substrate is then heated at a predetermined temperature, and reactions between the conductive material and the silicon substrate are detected using a SEM or an optical microscope.

摘要翻译： 通过提供硅衬底然后蚀刻所述硅衬底以在其中限定开口来评估阻挡材料相对于导电材料的屏障效能。 然后将阻挡材料沉积在开口中，随后沉积导电材料。 然后将硅衬底在预定温度下加热，并且使用SEM或光学显微镜检测导电材料和硅衬底之间的反应。

公开(公告)号：US06167753A

公开(公告)日：2001-01-02

申请号：US09226830

申请日：1999-01-07

申请人： Dong Chen ,  Edwin Flecha ,  James Michael Hammond ,  Kenneth Gilbert Roessler

发明人： Dong Chen ,  Edwin Flecha ,  James Michael Hammond ,  Kenneth Gilbert Roessler

IPC分类号： G01B734

CPC分类号： G01Q60/34 ,  G01Q60/30 ,  G01R29/0878 ,  G01R31/303 ,  Y10S977/851 ,  Y10S977/852

摘要： A scanning probe microscope operates in the manner of an atomic force microscope during intermittent periods of scanning motion, in which a sample surface is driven so that a scan line on the surface is moved past a probe tip being vibrated in engagement with the surface. Between these intermittent periods of scanning motion, the vibrating probe tip is moved out of engagement with the sample surface, so that the amplitude and phase shift of probe tip vibrations are determined by the gradient of a force field extending outward from the sample surface. Such a force field is established when the probe tip is attracted by, or repelled from, a magnetic or electric field at or near the sample surface. For each sample point, the system stores data representing the height of the sample surface and the force field.

公开(公告)号：US6161205A

公开(公告)日：2000-12-12

申请号：US193002

申请日：1998-11-16

申请人： Mark E. Tuttle

发明人： Mark E. Tuttle

IPC分类号： G01R31/01 ,  G01R31/28 ,  G01R31/303

CPC分类号： G01R31/303 ,  G01R31/01 ,  G01R31/2822 ,  G01R31/3025 ,  G06K7/0095 ,  G06K19/0701

摘要： A testing system evaluates one or more integrated circuit chips using RF communication. The system includes an interrogator unit with a radio communication range, and an IC chip adapted with RF circuitry positioned remotely from the interrogator unit, but within the radio communication range. The interrogator unit transmits a power signal to energize the IC chip during test procedures, and interrogating information for evaluating the operation of the IC chip. Test results are transmitted by the IC chip back to the interrogator unit for examination to determine whether the IC chip has a defect. In this manner, one or more IC chips can be evaluated simultaneously without physically contacting each individual chip.

摘要翻译： 测试系统使用RF通信来评估一个或多个集成电路芯片。 该系统包括具有无线电通信范围的询问器单元，以及适于远离询问器单元但在无线电通信范围内的RF电路的IC芯片。 询问器单元在测试过程期间发送功率信号以激励IC芯片，以及询问用于评估IC芯片的操作的信息。 测试结果由IC芯片发送回询问单元进行检查，以确定IC芯片是否有缺陷。 以这种方式，可以同时评估一个或多个IC芯片，而不物理地接触每个单独的芯片。

公开(公告)号：US6058497A

公开(公告)日：2000-05-02

申请号：US979607

申请日：1992-11-20

申请人： Mark E. Tuttle

发明人： Mark E. Tuttle

IPC分类号： G01R31/01 ,  G01R31/28 ,  G01R31/303 ,  G06F11/00

CPC分类号： G01R31/303 ,  G01R31/01 ,  G01R31/2822 ,  G01R31/3025 ,  G06K19/0701 ,  G06K7/0095

摘要： A testing system evaluates one or more integrated circuit chips using RF communication. The system includes an interrogator unit with a radio communication range, and an IC chip adapted with RF circuitry positioned remotely from the interrogator unit, but within the radio communication range. The interrogator unit transmits a power signal to energize the IC chip during test procedures, and interrogating information for evaluating the operation of the IC chip. Test results are transmitted by the IC chip back to the interrogator unit for examination to determine whether the IC chip has a defect. In this manner, one or more IC chips can be evaluated simultaneously without physically contacting each individual chip.