公开(公告)号：US09996654B2

公开(公告)日：2018-06-12

申请号：US14856578

申请日：2015-09-17

申请人： Wallace W Lin

发明人： Wallace W Lin

IPC分类号： G06F17/50 ,  H01L27/06 ,  H01L27/02

CPC分类号： G06F17/5081 ,  G06F17/5036 ,  G06F17/5063 ,  H01L27/0255 ,  H01L27/0617

摘要： A computer-implemented method capable of evaluating a plasma-induced charging effect to a transistor in a plasma-based process for a dielectric layer performed above the transistor on which a metal layer is formed is provided. The method may include receiving parameters relating to the transistor, receiving parameters relating to an interconnection, receiving parameters relating to the plasma-based process, assigning first potentials to terminals of the transistor, calculating second potentials at the terminals of the transistor, and determining a degradation state of the transistor according to the second potentials at the terminals of the transistor.

公开(公告)号：US09996646B2

公开(公告)日：2018-06-12

申请号：US15087502

申请日：2016-03-31

申请人： DELL PRODUCTS, LP

发明人： Bhyrav M. Mutnury ,  Arun R. Chada

IPC分类号： G06F17/50 ,  H05K3/00

CPC分类号： G06F17/5031 ,  G06F17/5036 ,  G06F17/5077 ,  G06F17/5081 ,  H05K3/0005

摘要： A method includes providing, on a printed circuit board, a first circuit trace having a first unit cell length and a second circuit trace having a second unit cell length, determining a time delay associated with the first unit cell length and the second unit cell length, estimating a floquet frequency associated with the time delay, where the floquet frequency is determined as f floquet = 1 2 ⁢ t delay , where ffloquet is the floquet frequency, and tdelay is the time delay, and comparing the estimated floquet frequency with a first interface frequency associated with the first trace.

公开(公告)号：US09996451B2

公开(公告)日：2018-06-12

申请号：US14860794

申请日：2015-09-22

申请人： International Business Machines Corporation

发明人： Pamela D. Andrejko ,  Andrew R. Freed ,  Richard A. Salmon ,  Charles S. Skinner

IPC分类号： G06F9/44 ,  G06F9/45 ,  G06F11/36 ,  G06F11/07 ,  G06F17/50 ,  G06Q10/06

CPC分类号： G06F11/3672 ,  G06F8/10 ,  G06F8/43 ,  G06F11/3664 ,  G06F11/3668 ,  G06F11/3684 ,  G06F17/5081 ,  G06Q10/06

摘要： Mechanisms are provided for evaluating test cases for testing a software product based on a requirements change. The mechanisms analyze a test case corpus to identify a plurality of first relationships between elements of test cases in the test case corpus and generate a test case relationship model based on the identified plurality of first relationships. The mechanisms receive a proposed requirements change to change one or more requirements of the software product and then perform a search of the test case relationship model to identify test case relationships corresponding to the proposed requirements change. The mechanisms identify a subset of test cases affected by the proposed requirements change and generate an output specifying the identified subset of test cases.

公开(公告)号：US09996000B2

公开(公告)日：2018-06-12

申请号：US15094226

申请日：2016-04-08

申请人： International Business Machines Corporation ,  Toppan Printing Co., Ltd.

发明人： Brian N. Caldwell ,  Yuki Fujita ,  Raymond W. Jeffer ,  James P. Levin ,  Joseph L. Malenfant, Jr. ,  Steven C. Nash

IPC分类号： H01L23/58 ,  G03F1/50 ,  G03F1/78 ,  G03F1/70 ,  G06F17/50 ,  G03F1/44

CPC分类号： G03F1/50 ,  G03F1/44 ,  G03F1/70 ,  G03F1/78 ,  G06F17/5081

摘要： Aspects of the present invention relate to a test photomask and a method for evaluating critical dimension changes in the test photomask. Various embodiments include a test photomask. The test photomask includes a plurality of cells having a varied density pattern. The plurality of cells include a first group of cells arranged along a first line, the first group of cells having a first combined density ratio. The plurality of cells also include a second group of cells arranged along a second line, the second group of cells having a second combined density ratio. In the plurality of cells, the second combined density ratio for the second group of cells is equal to the first combined density ratio of the first group of cells. The varied density pattern is configured to substantially neutralize fogging effects.

公开(公告)号：US09995998B2

公开(公告)日：2018-06-12

申请号：US15188753

申请日：2016-06-21

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Yi-Fan Chen ,  Tung-Heng Hsieh ,  Chin-Shan Hou ,  Yu-Bey Wu

IPC分类号： G03F1/36 ,  G06F17/50

CPC分类号： G03F1/36 ,  G06F17/5068 ,  G06F17/5081

摘要： A method includes receiving a layout of an integrated circuit (IC) device, the layout having an outer boundary and an inner boundary thereby defining a first region between the outer boundary and the inner boundary and placing a first plurality of dummy patterns in the first region, wherein the first plurality of dummy patterns is lithographically printable. The method further includes performing an Optical Proximity Correction (OPC) process, the first plurality of dummy patterns being position within the first region in such a way that prevents sub-resolution assist features from being inserted into the first region by the OPC process.

公开(公告)号：US09991249B2

公开(公告)日：2018-06-05

申请号：US15420514

申请日：2017-01-31

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Seong-Min Ryu ,  Hyo-Sig Won

IPC分类号： G06F17/00 ,  H01L27/02 ,  G06F17/50 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L27/0207 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  H01L21/7682 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295 ,  H01L28/00

摘要： A computer-implemented method of manufacturing an integrated circuit includes placing a plurality of standard cells that define the integrated circuit, selecting a timing critical path from among a plurality of timing paths included in the placed standard cells, and selecting at least one net from among a plurality of nets included in the timing critical path as at least one timing critical net. The method further includes pre-routing the at least one timing critical net with an air-gap layer, routing unselected nets, generating a layout using the pre-routed at least one timing critical net and the routed unselected nets, and manufacturing the integrated circuit based on the layout.

公开(公告)号：US09990455B1

公开(公告)日：2018-06-05

申请号：US15840549

申请日：2017-12-13

申请人： TactoTek Oy

发明人： Hasse Sinivaara ,  Tuomas Heikkilä ,  Antti Keränen

IPC分类号： G06F17/50 ,  G05B19/4099

CPC分类号： G06F17/5072 ,  G05B19/4099 ,  G05B2219/45031 ,  G06F17/5018 ,  G06F17/5081 ,  G06F2217/02 ,  G06F2217/04 ,  G06F2217/06 ,  G06F2217/12

摘要： An electronic arrangement for facilitating circuit layout design in connection with three-dimensional (3D) target designs, the arrangement including at least one communication interface for transferring data, at least one processor for processing instructions and other data, and a memory for storing the instructions and other data. The at least one processor being configured, in accordance with the stored instructions, to cause: obtaining and storing information in a data repository hosted by the memory, receiving design input characterizing 3D target design to be produced from a substrate, determining a mapping between locations of the 3D target design and the substrate, and establishing and providing digital output comprising human and/or machine readable instructions indicative of the mapping to a receiving entity, such as a manufacturing equipment, e.g. printing, electronics assembly and/or forming equipment.

公开(公告)号：US20180150592A1

公开(公告)日：2018-05-31

申请号：US15782232

申请日：2017-10-12

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Fong-Yuan CHANG ,  Jyun-Hao CHANG ,  Sheng-Hsiung CHEN ,  Ho Che YU ,  Lee-Chung LU ,  Ni-Wan FAN ,  Po-Hsiang HUANG ,  Chi-Yu LU ,  Jeo-Yen LEE

IPC分类号： G06F17/50 ,  H01L23/538 ,  H01L27/02

CPC分类号： G06F17/5081 ,  G06F17/5068 ,  G06F17/5072 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11811

摘要： A semiconductor device comprising active areas and a structure. The active areas are formed as predetermined shapes on a substrate and arranged relative to a grid having first and second tracks which are substantially parallel to corresponding orthogonal first and second directions; The active areas are organized into instances of a first row having a first conductivity and a second row having a second conductivity. Each instance of the first row and of the second row includes a corresponding first and second number predetermined number of the first tracks. The structure has at least two contiguous rows including: at least one instance of the first row; and at least one instance of the second row. In the first direction, the instance(s) of the first row have a first width and the instance(s) of the second row a second width substantially different than the first width.

公开(公告)号：US09984982B2

公开(公告)日：2018-05-29

申请号：US14916953

申请日：2014-02-19

申请人： ICTK CO., LTD.

发明人： Byong Deok Choi ,  Dong Kyue Kim

IPC分类号： H01L23/00 ,  G06F21/73 ,  G06F17/50 ,  H01L23/522 ,  H01L27/02 ,  H01L27/06 ,  H04L29/06 ,  G09C1/00 ,  H04L9/08

CPC分类号： H01L23/573 ,  G06F17/5072 ,  G06F17/5081 ,  G06F21/73 ,  G09C1/00 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/0629 ,  H04L9/0866 ,  H04L63/06 ,  H04L2209/12

摘要： The present invention relates to a device and method for generating an identification key using a process variation in a via process, and specifically the device for generating an identification key may include a first node provided in a semiconductor chip, a second node which is formed in a different layer from the first node, a via which is electrically shorted to the first node, and which is formed between the first node and the second node, the overlap distance between the second node and the via, in a pattern layout of the semiconductor chip, being adjusted to a value that is less than a threshold according to a design rule that ensures that the first node and the second node are shorted by the via, and a reader which provides an identification key by identifying whether the first node and the second node are shorted due to the via.

公开(公告)号：US09984194B2

公开(公告)日：2018-05-29

申请号：US14854247

申请日：2015-09-15

申请人： ARM LIMITED

发明人： Ramnath Bommu Sabbiah Swamy ,  Robert John Harrison

IPC分类号： G06F17/50 ,  H01L27/02 ,  H01L27/146

CPC分类号： G06F17/5081 ,  G06F17/5036 ,  G06F17/505 ,  G06F17/5072 ,  G06F2217/84 ,  H01L27/0207 ,  H01L27/14603

摘要： A computer-implemented method of integrated circuit design comprises: using a computer, producing an integrated circuit layout for multiple instances of a circuitry element, wherein interface components in one instance of said circuitry element communicate with complementary interface components in an adjacent instance of said circuitry element, said interface components being identical between said multiple instances; said producing step comprising: for one instance of said circuitry element, generating an integrated circuit layout for said one instance of said circuitry element on the basis of timing parameters of said complementary interface components with which said one instance communicates in use; detecting timing characteristics of said interface components of said one instance of said circuitry element; applying said detected timing characteristics as said timing parameters of said complementary interface components; and repeating said generating step.