公开(公告)号：US3925806A

公开(公告)日：1975-12-09

申请号：US52803074

申请日：1974-11-29

Applicant: BELL TELEPHONE LABOR INC

Inventor： STRAIN ROBERT JOSEPH ,  THORNBER KARVEL KUHN

IPC: G11C19/28 ,  G11C27/04 ,  H01L29/768 ,  H03H15/02 ,  H01L29/78

CPC classification number: H01L29/76816 ,  G11C19/285 ,  G11C27/04 ,  H03H15/02

Abstract: Distortion of signals in a semiconductor charge transfer device (CTD) section of N transfer stages, caused by incomplete transfer of electrical charges between successive stages in the device, is reduced by filtering the output signal of the device with an auxiliary CTD section serving as a filter for the N-stage CTD section. Advantageously, the ultimate (last) one of the stages in the auxiliary CTD section is built with an incomplete charge transfer coefficient characteristic which is substantially equal to the sum of the mutually substantially equal incomplete transfer characteristics of all other stages, both in the N-stage CTD section and in the other stages of the auxiliary CTD section. Thereby, the difference in transferred signal charge output from the ultimate and the penultimate (next to the last) auxiliary stages (at a selected time relative to the CTD time clock) yields a corrected output signal for the N-stage CTD section.

Abstract translation: 在设备的连续级之间的电荷的不完全传送引起的N个转移级的半导体电荷转移装置（CTD）部分中的信号失真通过用辅助CTD部分作为器件的器件的输出信号进行滤波来减少 滤波器用于N级CTD部分。 有利地，辅助CTD部分中的最后阶段的最后（最后一个）构建具有不完全的电荷传递系数特性，其基本上等于所有其它级的相互基本相等的不完全传递特性的和， 辅助CTD部分的其他阶段。 因此，从最终和倒数第二（下一个）辅助级（在相对于CTD时钟的选定时间）输出的传送信号电荷的差产生用于N级CTD部分的经校正的输出信号。

公开(公告)号：US3867645A

公开(公告)日：1975-02-18

申请号：US39355573

申请日：1973-08-31

Applicant: RCA CORP

Inventor： WEIMER PAUL KESSLER

IPC: G11C27/04 ,  H01L27/105 ,  H03F1/26 ,  H03F3/00 ,  H03F3/16 ,  H03F3/70 ,  H03H11/26 ,  H03H15/02 ,  G11C11/24 ,  G11C11/40 ,  G11C19/00 ,  H01L19/00

CPC classification number: H03F3/005 ,  G11C27/04 ,  H01L27/1055 ,  H03F1/26 ,  H03F3/16 ,  H03H15/02

Abstract: A charge transfer circuit for amplifying relatively low signal levels. The circuit includes a charge transfer register for propagating a charge signal along the register. Amplifying means are coupled along the register for sensing and amplifying the charge signal. The outputs of the amplifying means are then summed to produce an output signal having a high signal-to-noise ratio.

Abstract translation: 一种用于放大相对较低信号电平的电荷传输电路。 该电路包括用于沿寄存器传播电荷信号的电荷转移寄存器。 放大装置沿着寄存器耦合以感测和放大电荷信号。 然后将放大装置的输出相加以产生具有高信噪比的输出信号。

公开(公告)号：US3573442A

公开(公告)日：1971-04-06

申请号：US3573442D

申请日：1967-06-16

Applicant: SPERRY RAND CORP

Inventor： ANDEEN RICHARD E

IPC: G05D1/06 ,  G06G7/06 ,  G06G7/164 ,  G06G7/184 ,  G06G7/22 ,  H03H15/02

CPC classification number: G05D1/0607 ,  G06G7/06 ,  G06G7/164 ,  G06G7/184 ,  G06G7/22 ,  H03H15/02

Abstract: A hybrid analog-digital computer apparatus, particularly applicable in controlling complex servomechanisms such as aircraft flight control actuation and display systems, comprising a time shared or multiplexed operational amplifier adapted to receive analog signals from control system inputs and command sources through a large plurality of solid state switching devices at controllable gain levels and to supply outputs through a plurality of similar output switching devices to a plurality of analog storage devices, such as simple capacitors, the charges on the capacitors being fed back to the amplifier input in predetermined controlled manners for performing various control functions; the computer outputs being the resultant charges on one or more of said capacitors and being supplied to the actuation and/or display devices. Through predetermined control of the input and output switches, one or more input signals are selected and various computational operations thereon are performed as required for proper system control. The signals to be selected and the computations to be performed are under the control of a programmed digital memory, the sequential word and word bit outputs of which determine the sequence and orders respectively of switch operations and the signal gains required. The digital format of the program output and the high-speed operation of the solid-state switches provide extremely rapid sequencing of desired computations while the data always remains in analog form thereby retaining the precise resolution of analog computers while providing the high-speed capability of digital computers. Since all the computations are determined by the programmed memory, the computer is adaptable to control systems of widely different characteristics and complexity merely by the addition or deletion of switches and storage capacitors and by inserting the proper program into the memory. Hence, in terms of aircraft automatic flight control, a truly ''''universal'''' flight control system.

公开(公告)号：US20130120079A1

公开(公告)日：2013-05-16

申请号：US13735000

申请日：2013-01-06

Applicant: Broadcom Corporation

Inventor： Ahmadreza Rofougaran ,  Maryam Rofougaran

IPC: H01P9/00

CPC classification number: H01P9/00 ,  H01L23/66 ,  H01L2223/6677 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/0002 ,  H01L2924/15321 ,  H01L2924/19105 ,  H03H15/02 ,  H01L2924/00

Abstract: Methods and systems for a configurable finite impulse response (FIR) filter using a transmission line as a delay line are disclosed and may include selectively coupling one or more taps of a multi-tap transmission line to configure delays for one or more finite impulse response (FIR) filters to enable transmission and/or reception of signals. The delays may be configured based on a location of the one or more selectively coupled taps on the multi-tap transmission line. The FIR filters, which may include one or more stages, may be impedance matched to the selectively coupled taps. The multi-tap transmission line may be integrated on the chip, or a package to which the chip is coupled. The multi-tap transmission line may include a microstrip structure or a coplanar waveguide structure, and may include ferromagnetic material. The distortion of signals in the chip may be compensated utilizing the FIR filters.

Abstract translation: 公开了使用传输线作为延迟线的可配置有限脉冲响应（FIR）滤波器的方法和系统，并且可以包括选择性地耦合多抽头传输线的一个或多个抽头以配置一个或多个有限脉冲响应的延迟（ FIR）滤波器以实现信号的发送和/或接收。 可以基于多抽头传输线上的一个或多个选择性耦合抽头的位置来配置延迟。 可以包括一个或多个级的FIR滤波器可以与选择性耦合的抽头阻抗匹配。 多抽头传输线可以集成在芯片上，或者与芯片耦合到的封装上。 多抽头传输线可以包括微带结构或共面波导结构，并且可以包括铁磁材料。 可以利用FIR滤波器来补偿芯片中信号的失真。

公开(公告)号：US20130120058A1

公开(公告)日：2013-05-16

申请号：US13693590

申请日：2012-12-04

Applicant: Eric Nestler ,  Gustavo Castro

Inventor： Eric Nestler ,  Gustavo Castro

IPC: H03K5/00

CPC classification number: H03K5/00 ,  H03H15/02

Abstract: A filter provides high-pass coupling between circuits. The filter includes charge storage elements and switch elements coupling the charge storage elements. A controller is coupled to the switch elements for sequencing configurations of the switch elements in phases for each of a succession of sample periods to perform a time sampled continuous value signal processing of the input signal to form the processed signal. The sequenced configurations include a configuration in which a charge representing a value of the input signal is stored on a multiple of the charge storage elements, a configuration in which charge storage elements are coupled with the switch elements, and a set of one or more configurations that implement a scaling of a charge on one of the charge storage elements to be on one or more of the charge storage elements.

Abstract translation: 滤波器提供电路之间的高通耦合。 滤波器包括电荷存储元件和耦合电荷存储元件的开关元件。 控制器耦合到开关元件，用于对开关元件的配置进行排序，以对于连续的采样周期中的每一个进行相位，以执行输入信号的时间采样连续值信号处理以形成处理的信号。 顺序配置包括其中表示输入信号的值的电荷存储在电荷存储元件的倍数上的配置，其中电荷存储元件与开关元件耦合的配置，以及一组一个或多个配置 其中一个电荷存储元件上的电荷在一个或多个电荷存储元件上实现。

公开(公告)号：US20120306569A1

公开(公告)日：2012-12-06

申请号：US13490110

申请日：2012-06-06

Applicant: Eric Nestler ,  Jeffrey Venuti ,  Vladimir Zlatkovic ,  Kartik Nanda

Inventor： Eric Nestler ,  Jeffrey Venuti ,  Vladimir Zlatkovic ,  Kartik Nanda

IPC: H03K5/00

CPC classification number: H03K5/00 ,  H03H15/02

Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.

Abstract translation: 时域滤波方法采用无源电荷共享方式来实现无限脉冲响应滤波器。 将输入信号的延迟样本作为电荷存储在第一电容器阵列的电容器上，并且输出信号的延迟采样作为电荷存储在第二电容器阵列的电容器上。 输出由第一和第二阵列的电容器彼此无源耦合确定，并根据耦合的电容器上的总电荷来确定输出。 在一些示例中，在将输出存储在第二电容器阵列之前，将增益应用于总电荷。 在一些示例中，在耦合电容器之前，将电荷量化电路应用于存储在阵列上的电荷以形成输出。

公开(公告)号：US20100179977A1

公开(公告)日：2010-07-15

申请号：US12523393

申请日：2008-01-15

Applicant: James Wei ,  Dominique Morche

Inventor： James Wei ,  Dominique Morche

IPC: G06F17/17 ,  H03M1/66

CPC classification number: H03H15/02 ,  G11C27/026 ,  H03H19/004

Abstract: The invention relates to sampled filters with finite impulse response, or FIR filters.According to the invention, there is proposed an FIR filter comprising a transconductance amplifier with controllable gain (AGM), at least one sampling capacitor (CE) intended to receive an output current (di) from the amplifier and to periodically accumulate the charges produced by N successive samples of this current, and means for controlling the gain of the amplifier to give the amplifier a desired individual gain for each of the N samples. The weighting of the coefficients of the finite impulse response filter is effected through the transconductance gain of the amplifier and not through the value of a capacitor.

Abstract translation: 本发明涉及具有有限脉冲响应的采样滤波器或FIR滤波器。 根据本发明，提出了一种FIR滤波器，其包括具有可控增益（AGM）的跨导放大器，至少一个采样电容器（CE），用于从放大器接收输出电流（di），并周期性地累积由 该电流的N个连续采样，以及用于控制放大器的增益以给予放大器每个N个采样所需的单独增益的装置。 有限脉冲响应滤波器的系数的加权通过放大器的跨导增益而不是通过电容器的值来实现。

公开(公告)号：US20100171548A1

公开(公告)日：2010-07-08

申请号：US12690793

申请日：2010-01-20

Applicant: Eoin Ohannaidh ,  Stéphane Le Tual ,  Loïc Joet

Inventor： Eoin Ohannaidh ,  Stéphane Le Tual ,  Loïc Joet

IPC: H03K5/00

CPC classification number: H03H15/02 ,  H03H11/1291

Abstract: An analog finite impulse response (AFIR) filter including at least one variable transconductance block having an input for receiving an input voltage and being adapted to sequentially apply each of a plurality of transconductance levels to the input voltage during at least one of a plurality of successive time periods to generate an output current at an output of the variable transconductance block, the at least one variable transconductance block including a plurality of fixed transconductance blocks each receiving the input voltage and capable of being independently activated to supply the output current; and a capacitor coupled to the output of the variable transconductance block to receive the output current and provide an output voltage of the filter.

Abstract translation: 一种模拟有限脉冲响应（AFIR）滤波器，包括至少一个可变跨导块，其具有用于接收输入电压的输入，并且适于在多个连续的至少一个期间顺序地将多个跨导电平中的每一个施加到输入电压 在所述可变跨导块的输出处产生输出电流的所述时间周期，所述至少一个可变跨导块包括多个固定跨导块，每个固定跨导块接收所述输入电压并且能够被独立地激活以提供所述输出电流; 以及耦合到可变跨导块的输出的电容器，以接收输出电流并提供滤波器的输出电压。

公开(公告)号：US20050033792A1

公开(公告)日：2005-02-10

申请号：US10636094

申请日：2003-08-07

Applicant: Oliver Landolt

Inventor： Oliver Landolt

IPC: G06G7/02 ,  H03F3/60 ,  H03H7/30 ,  H03H11/26 ,  H03H15/02

CPC classification number: H03H11/26 ,  H03F3/604 ,  H03F3/605 ,  H03H7/30 ,  H03H15/02

Abstract: A delay line is constructed using a lossless (or low loss) transmission line which, in turn, can be constructed using an auxiliary conductor inductively coupled to the primary conductor. The auxiliary conductor is driven by the primary conductor through an active shunt network distributed along the transmission line. The auxiliary conductor is placed close enough to the primary conductor so that the two conductors have a substantial amount of mutual inductance compared to their self-inductance. In one embodiment, a combination of conductance and transconductance are used to cancel losses and control dispersion in the transmission line for high frequency signal transmission. In one embodiment, an FIR filter is constructed using the delay line.

Abstract translation: 延迟线使用无损（或低损耗）传输线构成，而传输线又可以使用感应耦合到主导体的辅助导体来构造。 辅助导体由主导体通过沿传输线分布的主动分流网络驱动。 辅助导体被放置得足够接近主导体，使得两个导体与其自感相比具有大量的互感。 在一个实施例中，使用电导和跨导的组合来消除损耗并控制用于高频信号传输的传输线中的色散。 在一个实施例中，使用延迟线构造FIR滤波器。

公开(公告)号：US06795001B2

公开(公告)日：2004-09-21

申请号：US10208674

申请日：2002-07-30

Applicant: Engel Roza

Inventor： Engel Roza

IPC: H03M300

CPC classification number: H03H15/02

Abstract: An analog FIR-filter comprising an asynchronous &Sgr;&Dgr; modulator (AM) generating amplitude-discrete time-continuous pulses coupled to a sequence of delay cells (C1 . . . Cn) for delaying the amplitude-discrete time-continuous pulses. One or more output devices (O1, On, S1, Sn, I1, In) for low pass filtering of the delayed amplitude-discrete time-continuous pulses.

Abstract translation: 模拟FIR滤波器包括异步SigmaDelta调制器（AM），其产生耦合到延迟单元序列（C1 ... Cn）的幅度离散时间连续脉冲，用于延迟幅度离散时间连续脉冲。 用于延迟振幅离散时间连续脉冲的低通滤波的一个或多个输出设备（O1，On，S1，Sn，I1，In）。