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41.发明授权
公开(公告)号：US5526527A
公开(公告)日：1996-06-11
申请号：US131210
申请日：1993-10-01
CPC分类号： H03L7/087 , H03L7/193 , H04B1/405 , H04M1/72502
摘要： Methods and apparatus for frequency synthesization are shown for generating an output signal of desired frequency. The frequency synthesizer includes an oscillator for generating an output signal at the desired frequency in response to a control signal. A first detector compares the output signal to a reference signal and generates a first difference signal representative of the differences, preferably in phase and frequency, between the output and the reference signals. A second detector compares the output signal to the reference signal and generates a second difference signal. A controller generates the control signal in response to either the first or second difference signal. A selector member selects between the first and second detectors to provide either the first or second control signal to the controller in response to a selection signal. A lock detector detects when the output signal and said reference signal are in a predetermined relation and generates the switch signal in response to the detection of the occurrence of such predetermined relation.
摘要翻译： 示出用于产生所需频率的输出信号的用于频率合成的方法和装置。 频率合成器包括用于响应于控制信号产生期望频率的输出信号的振荡器。 第一检测器将输出信号与参考信号进行比较，并产生表示输出和参考信号之间的差异，优选地在相位和频率上的第一差分信号。 第二检测器将输出信号与参考信号进行比较，并产生第二差分信号。 控制器响应于第一或第二差信号产生控制信号。 选择器构件在第一和第二检测器之间选择以响应于选择信号向控制器提供第一或第二控制信号。 锁定检测器检测输出信号和所述参考信号何时处于预定关系，并且响应于检测到这种预定关系的发生而产生开关信号。
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公开(公告)号：US5420545A
公开(公告)日：1995-05-30
申请号：US213935
申请日：1994-03-16
申请人： Craig M. Davis , David A. Byrd
发明人： Craig M. Davis , David A. Byrd
CPC分类号： H03L7/107 , H03L7/193 , H03L7/1972 , H03L7/1976 , H03L2207/04
摘要： A phase lock loop (PLL) circuit for controlling an oscillator includes a phase comparator, a loop filter, a reference converter and a feedback converter whose performance characteristics are dynamically controlled so as to provide a phase-locked output signal with both high frequency stepping resolution and low phase locking time. The phase comparator compares the relative phases of the reference and feedback signals, and outputs a phase difference signal representing such phase comparison. The loop filter, in accordance with a filter bandwidth dynamically selected by a filter control signal, filters the phase difference signal to provide a frequency control signal for a voltage controlled oscillator (VCO). The reference converter is a programmable frequency divider which, in accordance with a reference proportionality factor dynamically selected by a reference control signal, reduces the frequency of the PLL reference signal frequency used by the phase comparator. The feedback converter is another programmable frequency divider which, in accordance with a feedback proportionality factor dynamically determined by a feedback control signal, reduces the frequency of the VCO feedback signal frequency used by the phase comparator. Each combination of a selected filter bandwidth, a reference proportionality factor and a feedback proportionality factor corresponds to a different time interval within which phase lock is achieved.
摘要翻译： 用于控制振荡器的锁相环（PLL）电路包括相位比较器，环路滤波器，参考转换器和反馈转换器，其性能特性被动态地控制，以便提供具有高频步进分辨率的锁相输出信号 和低相位锁定时间。 相位比较器比较参考和反馈信号的相对相位，并输出表示这种相位比较的相位差信号。 环路滤波器根据滤波器控制信号动态选择的滤波器带宽，对相位差信号进行滤波，为压控振荡器（VCO）提供频率控制信号。 参考转换器是可编程分频器，其根据由参考控制信号动态选择的参考比例因子降低相位比较器使用的PLL参考信号频率的频率。 反馈转换器是另一个可编程分频器，其根据由反馈控制信号动态确定的反馈比例因子降低相位比较器使用的VCO反馈信号频率的频率。 选择的滤波器带宽，参考比例因子和反馈比例因子的每个组合对应于实现相位锁定的不同时间间隔。
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公开(公告)号：US5311152A
公开(公告)日：1994-05-10
申请号：US916999
申请日：1992-08-31
CPC分类号： H03C3/095 , H03C3/0925 , H03C3/0933 , H03C3/0941 , H03L7/193 , H03C2200/0079
摘要： A D.C. modulated phase locked oscillator (60, 80, 100, 140, 160, 190, 220, 264, or 290) includes a phase locking oscillator (70, 90, 128, 180, 192, 222, 266, or 292) and a D.C. modulator (72, 92, 130, 156, 182, 194, 224, 268, or 294). Both a forward path (14) and a feedback path (16) are D.C. modulated. D.C. modulation of the feedback path (16) optionally includes changing the frequency in the feedback path (16) as a function of the frequency of a modulation oscillator (64), changing the frequency in the feedback path (16) by a plurality of pulses for each cycle of the modulation oscillator (64), removing pulses from the feedback path (16), adding pulses to the feedback path (16), dividing the frequency in the feedback path (16) by higher and lower dividing ratios, preventing one cycle in the feedback path (16) from developing a "high" in the feedback path (16), holding a "high" in the feedback path ( 16) between two adjacent pulses, mixing quadrature frequencies with the feedback frequency in the feedback path (16), changing one input to a variable modulus divider (48) by means of a parallel adder (272), and using logic elements (148) to remove pulses from the feedback path (16).
摘要翻译： PCT No.PCT / US91 / 03602 Sec。 371日期：1992年8月31日 102（e）日期1992年8月31日PCT提交1991年5月22日PCT公布。 WO91 / 18444 PCT出版物 日前，1991年11月28日，DC调制锁相振荡器（60,80,100,140,160,190,226,290或290）包括锁相振荡器（70,90,128,180,192,222） ，266或292）和DC调制器（72,92,130,156,182,194,224,268或294）。 正向路径（14）和反馈路径（16）都被调制。 反馈路径（16）的DC调制可选地包括根据调制振荡器（64）的频率来改变反馈路径（16）中的频率，将反馈路径（16）中的频率改变多个脉冲 对于调制振荡器（64）的每个周期，从反馈路径（16）去除脉冲，向反馈路径（16）添加脉冲，将反馈路径（16）中的频率除以更高和更低的分频比，防止一个 在反馈路径（16）中循环在反馈路径（16）中产生“高”，在两个相邻脉冲之间的反馈路径（16）中保持“高”，将正交频率与反馈路径中的反馈频率混合 （16），通过并行加法器（272）将一个输入改变为可变模数分频器（48），并且使用逻辑元件（148）去除来自反馈路径（16）的脉冲。
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44.发明授权Radio communication apparatus free from interference between local signal and transmission signal 失效无线通信装置不受本地信号与传输信号之间的干扰
公开(公告)号：US4864634A
公开(公告)日：1989-09-05
申请号：US268253
申请日：1988-11-07
摘要： A radio communication apparatus capable of carrying out transmission and reception of signals at a time has a frequency synthesizer and a frequency modulator both in novel structures for removing interference between a local signal and a transmission signal. The frequency synthesizer has a local oscillator controlled by a first phase comparator for phase-comparing a frequency divided output of the local oscillator and a reference frequency signal to provide a local signal. The frequency division of the output of the local oscillator is effectd by a first frequency divider for dividing the frequency of the output of the local oscillator and a variable division ratio frequency divider for dividing the frequency of the output of the first frequency divider. The frequency modulator has a transmission oscillator controlled by a second phase comparator for phase-comparing the output of the first frequency divider and a frequency divided output of the transmission oscillator to provide a transmission signal. The frequency division of the output of the transmission oscillator is effected by a second frequency divider.
摘要翻译： 能够一次执行信号的发送和接收的无线电通信装置具有用于消除本地信号和发送信号之间的干扰的新颖结构的频率合成器和频率调制器。 频率合成器具有由第一相位比较器控制的本地振荡器，用于对本地振荡器的分频输出和参考频率信号进行相位比较，以提供本地信号。 本地振荡器的输出的分频由用于分频本地振荡器的输出频率的第一分频器和用于分频第一分频器的输出频率的可分分频分频器来实现。 频率调制器具有由第二相位比较器控制的发送振荡器，用于对第一分频器的输出和发送振荡器的分频输出进行相位比较，以提供发送信号。 传输振荡器的输出的分频由第二分频器实现。
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公开(公告)号：US4633194A
公开(公告)日：1986-12-30
申请号：US277396
申请日：1981-06-25
CPC分类号： H03K23/667 , H03L7/193
摘要： The frequency divider includes a first or prescaling counter which selects between first and second frequency division factors, in response to a first control signal, and then divides an input signal frequency responsive to the first control signal. A second and programmable counter frequency divides the output of the first or prescaling counter by a third frequency-division factor. A third and programmable counter frequency divides the output of the first counter by a fourth frequency-division factor which is smaller than the third frequency-division factor. A switching control circuit then converts the output of the third counter and supplies the converted signal to the first counter, as the first control signal. The digital frequency divider is suitable for use a part of a phase-locked loop frequency synthesizer.
摘要翻译： 分频器包括响应于第一控制信号在第一和第二分频因子之间进行选择的第一或预分频计数器，然后响应于第一控制信号对输入信号频率进行分频。 第二和可编程计数器频率将第一或预分频计数器的输出除以第三分频因子。 第三和可编程计数器频率将第一计数器的输出除以小于第三分频因子的第四分频因子。 开关控制电路然后转换第三计数器的输出，并将转换的信号作为第一控制信号提供给第一计数器。 数字分频器适用于锁相环频率合成器的一部分。
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公开(公告)号：US4484153A
公开(公告)日：1984-11-20
申请号：US251559
申请日：1981-04-06
申请人： Jaime A. Borras , Ruben J. Gonzalez , Daniel M. Smith , Jose I. Suarez , Alan M. Victor , Alfred B. Wieczorek
发明人： Jaime A. Borras , Ruben J. Gonzalez , Daniel M. Smith , Jose I. Suarez , Alan M. Victor , Alfred B. Wieczorek
IPC分类号： H03C3/09 , H03C3/22 , H03D13/00 , H03J5/02 , H03K23/66 , H03L7/08 , H03L7/193 , H03L7/199 , H04B1/40 , H03L7/18
CPC分类号： H03K21/38 , H03C3/0933 , H03C3/0941 , H03C3/0958 , H03C3/0966 , H03C3/227 , H03D13/005 , H03J5/0281 , H03K23/667 , H03L7/0802 , H03L7/193 , H03L7/199 , H04B1/405
摘要： In a frequency synthesizer phase locked loop including a reference oscillator, a variable reference divider (.div.M), a sample and hold phase detector, a loop filter, a voltage controlled oscillator and a variable divider (.div.N), a voltage converter for controlling the voltage of a control input to the voltage controlled oscillator is disclosed. In the preferred embodiment, the voltage converter has its input connected to the output of a first reference divider in the variable reference divider (.div.M) and its output connected to a control input (varactor diode) of the voltage controlled oscillator. The voltage converter clamps the divider reference signal from the first reference divider and provides a negative voltage level output to bias the varactor diode of the voltage controlled oscillator. Thus, the tuning range of the frequency synthesizer is increased.
摘要翻译： 在包括参考振荡器，可变参考分频器（DIVIDED M），采样和保持相位检测器，环路滤波器，压控振荡器和可变分频器（DIVIDED N）的频率合成器锁相环中，用于控制 公开了对压控振荡器的控制输入的电压。 在优选实施例中，电压转换器的输入连接到可变参考分压器（DIVIDED M）中的第一参考分压器的输出，其输出连接到压控振荡器的控制输入（变容二极管）。 电压转换器钳位来自第一参考分压器的分频器参考信号，并提供负电压电平输出以偏压压控振荡器的变容二极管。 因此，频率合成器的调谐范围增加。
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公开(公告)号：US4357527A
公开(公告)日：1982-11-02
申请号：US6490
申请日：1979-01-25
申请人： Tadashi Kojima
发明人： Tadashi Kojima
CPC分类号： H03L7/193 , H03J5/0272 , H03K23/667
摘要： Disclosed is a programmable divider which is provided with high- and low-speed dividers and, and a pulse interval extender. The extender increases or decreases to a predetermined degree the interval or width of pulses divided by the high-speed divider. Then, a dividing ratio of a divider circuit formed of the high- and low-speed dividers and concatenated with each other is varied within one dividing cycle.
摘要翻译： 公开了一种可编程分频器，其具有高速和低速分频器以及脉冲间隔延长器。 延长器将由高速分压器分开的脉冲的间隔或宽度增加或减小到预定的程度。 然后，由高分压器和低速分压器形成的并联的分压电路的分频比在一个分频周期内变化。
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48.发明授权
公开(公告)号：US4258333A
公开(公告)日：1981-03-24
申请号：US44728
申请日：1979-06-01
申请人： Pierre Demuliere , Pierre Heins
发明人： Pierre Demuliere , Pierre Heins
CPC分类号： H03L7/113 , H03L7/1974 , H03L7/193
摘要： This synthesizer comprises a phase-locked main loop, a frequency searching loop, a first digital loop for forming steps equal to the reference frequency F and a second digital loop for forming steps equal to the frequency F/Q, Q being an integer. According to the invention this synthesizer further comprises a third digital loop which acts on the setting of the steps having value F for forming the steps having a frequency F/R, R being an integer near Q. The elementary frequency step of the synthesizer has the frequency value .vertline.F/Q-F/R.vertline. or a value equal to a submultiple of the last-mentioned value. This spurious modulation at the frequency OR/.vertline.Q-R.vertline. F of the output signal of the phase comparator has an amplitude which is sufficiently low to make filtering unnecessary.
摘要翻译： 该合成器包括锁相主环路，频率搜索环路，用于形成等于参考频率F的步长的第一数字环路和用于形成等于频率F / Q的步长的第二数字环路，Q为整数。 根据本发明，该合成器还包括第三数字环路，其作用于具有值F的步骤的设置，用于形成具有频率F / R的步骤，R是接近Q的整数。合成器的基本频率步长具有 频率值| F / QF / R |或等于最后提到的值的一个数的值。 在相位比较器的输出信号的频率OR / | Q-R | F处的这种杂散调制具有足够低的幅度，从而不需要滤波。
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公开(公告)号：US4186342A
公开(公告)日：1980-01-29
申请号：US848559
申请日：1977-11-04
申请人： Robert R. Kyle
发明人： Robert R. Kyle
CPC分类号： H05K5/0017 , H04B1/03 , H04B1/401 , H03L7/193 , H04B2001/3894
摘要： An improved marine radio telephone is disclosed which has a housing having an angular opening suitable for either above or below eye level installation and a chassis having printed wiring board support members including a tiltable front panel support member for adapting the front panel to correspond to the position of the housing when mounted therein and a rear support member for supporting the transmitter board and heat sink for improved heat dissipation. The front panel includes a keyboard having keys for selecting digits 0 to 9, an emergency channel, and weather channels, a display for displaying the channel selected, control knobs for volume and squelch control, and switches for power and U.S.A. or international channel selection. The printed wiring boards include a front panel board, a digital input/output and power board, a frequency synthesizer board, a receiver board and a transmitter board. The front panel board sends operating signals to and receives outputs from the other boards. The digital input/output board includes a digital detector means for producing binary coded numbers representative of the keys pressed, a load control means for alternately loading the binary coded numbers into a tens register and a units register, an illegal channel detector connected to the tens and units registers for detecting an improper channel selection, and a memory connected to the units register and producing in response to binary coded numbers for legal channels a synthesizer address code for the channel selected. The synethesizer board is connected to the digital input/output and power board to provide, in response to the synthesizer address code, a local oscillator signal for the receiver clearing receiver operation and an audio modulated signal for transmission during transmitter operation. A phase lock loss signal is produced for preventing illegal operation. The receiver board includes an improved squelch circuit which provides for fine tuning to eliminate noise without unnecessarily reducing the audio signal.
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公开(公告)号：US4121162A
公开(公告)日：1978-10-17
申请号：US695875
申请日：1976-06-14
CPC分类号： H03L7/193 , H03J5/0281 , H03J7/065
摘要： A phase locked loop circuit for use in an automatic frequency synthesizing system. The system includes a programmer circuit which is responsive to a channel number input signal and generates a first digital control signal which is representative of the selected channel number and a second digital control signal which is representative of a predetermined group of channel numbers. A programmable divider is controlled by the programming circuit and generates a digital output signal which causes the phase locked loop circuit to generate a desired system output frequency corresponding to the selected channel number input signal. The phase locked loop circuit includes automatic fine tuning and manual fine tuning features.
摘要翻译： 一种用于自动频率合成系统的锁相环电路。 该系统包括对通道号输入信号作出响应的编程器电路，并产生代表所选择的通道号的第一数字控制信号和表示预定的通道组数的第二数字控制信号。 可编程分频器由编程电路控制，并产生数字输出信号，使得锁相环电路产生对应于所选频道号输入信号的所需系统输出频率。 锁相环电路包括自动微调和手动微调功能。
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