公开(公告)号：US20190113476A1

公开(公告)日：2019-04-18

申请号：US16143897

申请日：2018-09-27

Applicant: Analog Devices Global Unlimited Company

Inventor： Michael Coln ,  Mark Daniel de Leon Alea

IPC: G01N27/327 ,  G01N33/487 ,  G01N33/497 ,  G01N27/414

Abstract: Embodiments of the present disclosure relate to various methods and example systems for carrying out analog-to-digital conversion of data acquired by arrays of nanogap sensors. The nanogap sensors described herein may operate as molecular sensors to help identify chemical species through electrical measurements using at least a pair of electrodes separated by a nanogap. In general, the methods and systems proposed herein rely on digitizing the signal as the signal is being integrated, and then integrating the digitized results. With such methods, the higher sample rate used in the digitizer reduces the charge per quantization and, therefore, the size of sampling capacitors used. Consequently, sampling capacitors may be made factors of magnitude smaller, requiring less valuable space on a chip compared to sampling capacitors used in conventional nanogap sensor arrays.

公开(公告)号：US10256831B2

公开(公告)日：2019-04-09

申请号：US15271697

申请日：2016-09-21

Applicant: Analog Devices Global

Inventor： Sandeep Monangi ,  Mahesh Madhavan

IPC: H03M1/00 ,  H03M1/06 ,  H03M1/12 ,  H03M1/38 ,  H03M3/00 ,  H03M1/10 ,  H03M1/46

Abstract: A successive approximation register analog to digital converter (SAR ADC) is provided in which impact of dielectric absorption is reduced with a correction circuit configured to adjust a present digital code value signal based at least in part upon a previous digital code value signal, an acquisition time and temperature.

公开(公告)号：US10250194B2

公开(公告)日：2019-04-02

申请号：US15085477

申请日：2016-03-30

Applicant: Analog Devices Global

Inventor： Patrick Pratt ,  Joseph Bradford Brannon ,  Ronald Dale Turner

IPC: H03F3/04 ,  H03F1/02 ,  H03F1/32 ,  H03F3/19 ,  H03F3/24 ,  H04B1/04 ,  H03F3/21 ,  H03K5/15

Abstract: An envelope tracking scheme can be used, such as to modulate a supply node of a power amplifier circuit to improve efficiency. For example, a magnitude or amplitude envelope of a signal to be modulated can be scaled and used to drive a node, such as a drain, of the power amplifier circuit. An envelope tracking signal can be generated such as having a bandwidth that is compressed as compared to a full-bandwidth envelope signal. A peak-value “look ahead” technique can be used, for example, so that amplitude compression or clipping of the transmit signal is suppressed when the bandwidth-compressed envelope tracking signal is used to modulate a supply node of the power amplifier used to amplify the transmit signal.

公开(公告)号：US10234288B2

公开(公告)日：2019-03-19

申请号：US14853265

申请日：2015-09-14

Applicant: Analog Devices Global Unlimited Company

Inventor： Siddharth Tallur ,  Sunil Ashok Bhave

IPC: G01C19/5677 ,  G01C19/5698

Abstract: A BAW gyroscope is configured to operate with two pairs of orthogonal modes instead of a single pair in order to mitigate the impact of changes in gaps (e.g., introduced from external stresses such as thermal gradients, external shocks, mechanical stress/torque, etc.). Specifically, the BAW gyroscope resonator is configured to be simultaneously driven to resonate with a two disparate resonant modes (referred to herein as the “fundamental” mode and the “compound” mode), with the same set of drive electrodes used to drive both resonant modes (i.e., all of the drive electrodes are used to drive the two drive modes). When the sensor experiences external rotation, energy couples from the driven modes of vibration to two corresponding orthogonal sense modes via the Coriolis force. The same set of sense electrodes is used to sense both sense modes (i.e., all of the sense electrodes are used to sense the two sense modes). The fundamental mode is differential with respect to the electrodes, while the compound mode is seen as common-mode with respect to the electrodes. Thus, differential gap change will impact offset of rate measured with the fundamental mode only, while common-mode gap change will impact offset of rate measured with the compound mode only.

公开(公告)号：US20190079117A1

公开(公告)日：2019-03-14

申请号：US15700867

申请日：2017-09-11

Applicant: Analog Devices Global Unlimited Company

Inventor： Jonathan Ephraim David Hurwitz ,  William Michael James Holland ,  Seyed Amir Ali Danesh

IPC: G01R15/20 ,  G01R19/00 ,  G01R15/14 ,  G01R21/08 ,  G01R33/36 ,  G01R1/20

Abstract: A measurement circuit is arranged to make several measurements, either at different times or in respect of different frequency components of currents measured by current sensors in respective phases of a multiphase supply system. The measurements are then used to correct for discrepancies in the transfer function of the sensors.

公开(公告)号：US10212261B2

公开(公告)日：2019-02-19

申请号：US15095004

申请日：2016-04-08

Applicant: ANALOG DEVICES GLOBAL

Inventor： Prakash Govindaraju ,  Hans Waldmann ,  Shankar S. Malladi

IPC: H04W24/02 ,  H04L29/06 ,  H04L29/08 ,  H04W40/00 ,  H04W4/38 ,  H04W80/04

Abstract: Wireless sensor nodes for enabling network connectivity in a wireless sensor network system are disclosed herein. An exemplary method includes receiving a Lightweight Machine-to-Machine (LWM2M) network packet from a network node over a network; using a media access control (MAC) layer to route the LWM2M network packet to a sensor node when a destination Internet Protocol (IP) address specified in the LWM2M network packet matches a virtual IP address; and using a network layer to route the LWM2M network packet to the sensor node when the destination IP address does not match a virtual IP address.

公开(公告)号：US20190052281A1

公开(公告)日：2019-02-14

申请号：US15674985

申请日：2017-08-11

Applicant: Analog Devices Global

Inventor： Frederick Carnegie Thompson ,  Varun Agrawal ,  Jose Barreiro Silva ,  Declan M. Dalton

IPC: H03M1/08 ,  H03M1/74 ,  H03M1/06 ,  H03M1/12 ,  H03L7/089 ,  H03K5/1252 ,  H03K7/06 ,  H04L27/06

CPC classification number: H03M1/0836 ,  H03K5/1252 ,  H03K7/06 ,  H03L7/08 ,  H03L7/0893 ,  H03L2207/50 ,  H03M1/0621 ,  H03M1/1245 ,  H03M1/747 ,  H03M3/43 ,  H03M3/458 ,  H04L27/066

Abstract: This disclosure relates to data converters for electronic systems. An example system includes a primary analog to digital converter (ADC) circuit, a slope calculation circuit, a digital phase lock loop (DPLL) circuit, a sampling error circuit, and a summing circuit. The primary ADC circuit samples an input signal and produces a digital output signal representative of the input signal. The slope calculation circuit generates a digital slope signal representative of slope of the input signal, and the DPLL circuit provides a sampling clock signal to the primary ADC circuit. The sampling error circuit generates a sampling error signal representative of sampling error by the primary ADC circuit using the digital slope signal and the sampling clock signal. The summing circuit receives the sampling error signal and the digital output signal of the primary ADC circuit and generates an adjusted digital output signal representative of the input signal.

公开(公告)号：US20190039883A1

公开(公告)日：2019-02-07

申请号：US15666475

申请日：2017-08-01

Applicant: Analog Devices Global

Inventor： Baoxing Chen ,  William Allan Lane ,  Marc T. Dunham

IPC: B81B7/00 ,  H01L23/427 ,  H01L23/367

Abstract: A monolithic vapor chamber heat dissipating device uses a phase change liquid and one or more wicks to dissipate heat from a heat-generating system. The phase change liquid and one or more wicks may be directly coupled to the heat-generating system, or may be coupled to an intermediate evaporator substrate. The phase change liquid vaporizes as it absorbs heat from the heat-generating system. When the vapor rises and encounters a condenser substrate, the vapor condenses and transfers the heat to the condenser substrate. The condensed vapor is drawn by gravity and the one or more wicks to the phase change liquid coupled to the heat-generating system.

公开(公告)号：US10200055B2

公开(公告)日：2019-02-05

申请号：US15863313

申请日：2018-01-05

Applicant: Analog Devices Global

Inventor： Peter Enright ,  Martina Mincica ,  Fergus Downey

IPC: H03M1/66 ,  H03M1/08 ,  H03M1/10

Abstract: Techniques and related circuits are disclosed and can be used to characterize glitch performance of a digital-to-analog (DAC) converter circuit in a rapid and repeatable manner, such as for use in providing an alternating current (AC) glitch value specification. A relationship can exist between a glitch-induced DAC output offset value and a DAC circuit input event rate. A relationship between the event rate (e.g., update rate) and the DAC output offset can be used to predict an offset value based at least in part on update rate or to estimate a corresponding glitch impulse area. In particular, a value representing glitch impulse area can be obtained by use of a hardware integration circuit without requiring use of a digitized time-series of glitch event waveforms.

公开(公告)号：US10171102B1

公开(公告)日：2019-01-01

申请号：US15865742

申请日：2018-01-09

Applicant: Analog Devices Global Unlimited Company

Inventor： Hajime Shibata ,  Yunzhi Dong ,  Zhao Li ,  Trevor Clifford Caldwell ,  Wenhua William Yang

IPC: H03M1/12 ,  H03M3/00 ,  H03M1/66 ,  H03M1/06

Abstract: A linear continuous-time (CT) delaying summation block is one of the key building blocks for CT multi-stage analog-to-digital converters (ADCs) such as CT pipeline ADCs and CT multi-stage delta-sigma (MASH) ADCs. The CT summation block is typically used on a stage of a CT multi-stage ADC to subtract a digital-to-analog converter (DAC) output signal from an analog input signal of the stage. Rather than using a current-mode summation, the CT delaying summation block can be implemented with voltage-mode summation.