公开(公告)号：US20240311234A1

公开(公告)日：2024-09-19

申请号：US18676811

申请日：2024-05-29

Applicant: Intel Corporation

Inventor： David M. Durham ,  Sergej Deutsch ,  Karanvir Grewal

IPC: G06F11/10 ,  H04L9/08

CPC classification number: G06F11/1044 ,  H04L9/0816

Abstract: The technology disclosed herein includes a memory to store a plurality of pages, a page of the plurality of pages configured as one of a trusted execution environment (TEE) configuration and a non-TEE configuration, and a memory controller to attempt to access the page using a memory address and the TEE configuration and generate a first error correcting code (ECC); and when data for the first ECC is at least one of correct and correctable by ECC for the attempt to access the page using the TEE configuration, attempt to access the page using the memory address and the non-TEE configuration and generate a second ECC, and when data the second ECC is at least one of correct and correctable by ECC for the attempt to access the page using the non-TEE configuration, store the memory address as an unknown cacheline address.

公开(公告)号：US20240307773A1

公开(公告)日：2024-09-19

申请号：US18478201

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Selvakumar Panneer ,  John Feit ,  Sarthak Rajesh Shah ,  SungYe Kim ,  Nilesh Jain

IPC: A63F13/52

CPC classification number: A63F13/52 ,  A63F2300/66

Abstract: Described herein is a technique to enhance the responsiveness of gameplay for a 3D gaming application while maintaining the ability to enqueue multiple frames for processing on the GPU. Each frame or a set of workloads within a frame is submitted to the GPU with predication, such that the indicated rendering and resource manipulation commands are not actually performed if the predication condition is enabled. A low latency command can be submitted to the GPU via a copy engine command queue. The command will cause the copy engine to enable or disable predication for command buffers in the command queue. When predication for queued command buffers is enabled, command buffers for workloads that are not related to the workload that is generated in response to the user input are bypassed. High priority command buffers that include workloads generated in response to user input can then be executed immediately.

公开(公告)号：US12096566B2

公开(公告)日：2024-09-17

申请号：US16157185

申请日：2018-10-11

Applicant: Intel Corporation

Inventor： Tyler Leuten

IPC: H05K3/00 ,  H05K1/11 ,  H05K1/18

CPC classification number: H05K3/0097 ,  H05K1/117 ,  H05K1/181 ,  H05K3/0026 ,  H05K2201/09045 ,  H05K2201/09154 ,  H05K2201/09972 ,  H05K2201/10522 ,  H05K2203/308

Abstract: Embodiments disclosed herein include a printed circuit board (PCB) with a non-uniform thickness and methods of fabricating such PCBs. In an embodiment, the PCB comprises a connector region with a top surface and a bottom surface, and a component region with a top surface and a bottom surface. In an embodiment, the bottom surface of the connector region is coplanar with the bottom surface of the component region. In an embodiment the top surface of the connector region is not coplanar with the top surface of the component region.

公开(公告)号：US12096458B2

公开(公告)日：2024-09-17

申请号：US17508163

申请日：2021-10-22

Applicant: Intel Corporation

Inventor： Honglei Miao

IPC: H04W56/00 ,  H04L1/1812 ,  H04L5/00 ,  H04W72/02 ,  H04W72/0446 ,  H04W72/0453 ,  H04W72/1273 ,  H04W72/23 ,  H04W72/30

CPC classification number: H04W72/30 ,  H04L1/1819 ,  H04L5/0053 ,  H04W72/02 ,  H04W72/0446 ,  H04W72/0453 ,  H04W72/1273 ,  H04W72/23

Abstract: An apparatus and system to provide MBS transmissions are described. MBS-specific common resource pools are provided for simultaneously reception of multiple MBS transmissions. The pools have non/partial/fully-overlapped frequency resources in a UE-specific downlink BWP. A control resource set is associated with the pool to allocate the MBS downlink grant as well as the MBS data resource can within the pool. A slot contains multiple mini-slots that contain an MBS transmission, a unicast PDSCH transmission, and a second unicast PDSCH transmission for a different UE or to retransmit the MBS transmission. Control channel search spaces allocate different DCI formats in the slot.

公开(公告)号：US12095973B2

公开(公告)日：2024-09-17

申请号：US17131433

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Bogna Bylicka ,  Pawel Pieniazek ,  Jakub Powierza

IPC: H04N13/282 ,  G06T5/50 ,  H04N13/243 ,  H04N13/275

CPC classification number: H04N13/282 ,  G06T5/50 ,  H04N13/243 ,  H04N13/275

Abstract: Example image processing methods, apparatus, systems and articles of manufacture (e.g., computer readable media) to implement multi-object multi-view association are disclosed. Examples disclosed herein obtain initial two-dimensional (2D) bounding boxes of detected objects in multiple images of a scene from multiple cameras, generate a plurality of three-dimensional (3D) bounding boxes potentially corresponding to one or more objects to be tracked, and generate a weight that represents a strength of association between two detected objects respectively in two images of the multiple images. The weight is based on projection of one of the 3D bounding boxes back to at least one of the two images to generate a re-projection 2D bounding box.

公开(公告)号：US12095189B2

公开(公告)日：2024-09-17

申请号：US17134099

申请日：2020-12-24

Applicant: Intel Corporation

Inventor： Richard S. Perry ,  Robert Schum

IPC: H01R12/00 ,  G06F1/18 ,  H01R12/52 ,  H01R12/70 ,  H01R12/72 ,  H01R12/73 ,  G06F1/16

CPC classification number: H01R12/727 ,  G06F1/185 ,  H01R12/523 ,  H01R12/7047 ,  H01R12/732 ,  G06F1/1635

Abstract: A board-to-board connector includes electrical leads to bridge from one board to another board, to interconnect pads on one surface of the boards. The boards can interconnect while one board is vertically offset from the other board with a top mount connector. The connector includes a lead frame having the electrical leads and the connector includes an alignment frame to hold the lead frame. The lead frame includes leads that have contact arms that are vertically offset from each other. The connector includes a conductive case to secure over the alignment frame. The connector includes screw holes to allow screws to secure the connector in place against the boards and ensure electrical connection between the pads on the two boards through the electrical leads of the connector. The alignment frame includes posts to mate with alignment holes in the boards.

公开(公告)号：US12094822B2

公开(公告)日：2024-09-17

申请号：US16950240

申请日：2020-11-17

Applicant: Intel Corporation

Inventor： Guillaume Bouche ,  Andy Chih-Hung Wei ,  Changyok Park

IPC: H01L23/528 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L23/5286 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/823871 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0924 ,  H01L29/0673 ,  H01L29/66795 ,  H01L29/785

Abstract: Transistor arrangements fabricated by forming a metal gate cut as an opening that is non-selective to the gate sidewalls are disclosed. The etch process may be used to provide a power rail if the opening is at least partially filled with an electrically conductive material. Once an electrically conductive material has been deposited within the opening to form a power rail, recessing such a material in portions of the power rail that face gate stacks of various transistors may provide further improvements in terms of reduced parasitic capacitance. A mask for a trench contact to be used to electrically couple the power rail to a S/D region of a transistor may be used as a mask when the electrically conductive material of the power rail is recessed to realize a via that is self-aligned to the trench contact.

公开(公告)号：US12093836B2

公开(公告)日：2024-09-17

申请号：US17129521

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Mattias Marder ,  Estelle Aflalo ,  Avrech Ben-David ,  Shauharda Khadka ,  Somdeb Majumdar ,  Santiago Miret ,  Hanlin Tang

IPC: G06N3/10 ,  G06N3/045 ,  G06N3/086

CPC classification number: G06N3/10 ,  G06N3/045 ,  G06N3/086

Abstract: Automatic multi-objective hardware optimization for processing a deep learning network is disclosed. An example of a storage medium includes instructions for obtaining client preferences for a plurality of performance indicators for processing of a deep learning workload; generating a workload representation for the deep learning workload; providing the workload representation to machine learning processing to generate a workload executable, the workload executable including hardware mapping based on the client preferences; and applying the workload executable in processing of the deep learning workload.

公开(公告)号：US12093210B2

公开(公告)日：2024-09-17

申请号：US17430574

申请日：2020-03-14

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Aravindh Anantaraman ,  Elmoustapha Ould-Ahmed-Vall ,  Joydeep Ray ,  Mike Macpherson ,  Valentin Andrei ,  Nicolas Galoppo Von Borries ,  Varghese George ,  Subramaniam Maiyuran ,  Vasanth Ranganathan ,  Jayakrishna P S ,  K Pattabhiraman ,  Sudhakar Kamma

IPC: G06F15/78 ,  G06F7/544 ,  G06F7/575 ,  G06F7/58 ,  G06F9/30 ,  G06F9/38 ,  G06F9/50 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/80 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06N3/08 ,  G06T15/06

CPC classification number: G06F15/7839 ,  G06F7/5443 ,  G06F7/575 ,  G06F7/588 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30065 ,  G06F9/30079 ,  G06F9/3887 ,  G06F9/5011 ,  G06F9/5077 ,  G06F12/0215 ,  G06F12/0238 ,  G06F12/0246 ,  G06F12/0607 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0875 ,  G06F12/0882 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/0893 ,  G06F12/0895 ,  G06F12/0897 ,  G06F12/1009 ,  G06F12/128 ,  G06F15/8046 ,  G06F17/16 ,  G06F17/18 ,  G06T1/20 ,  G06T1/60 ,  H03M7/46 ,  G06F9/3802 ,  G06F9/3818 ,  G06F9/3867 ,  G06F2212/1008 ,  G06F2212/1021 ,  G06F2212/1044 ,  G06F2212/302 ,  G06F2212/401 ,  G06F2212/455 ,  G06F2212/60 ,  G06N3/08 ,  G06T15/06

Abstract: Methods and apparatus relating to techniques for data compression. In an example, an apparatus comprises a processor receive a data compression instruction for a memory segment; and in response to the data compression instruction, compress a sequence of identical memory values in response to a determination that the sequence of identical memory values has a length which exceeds a threshold. Other embodiments are also disclosed and claimed.

公开(公告)号：US20240305969A1

公开(公告)日：2024-09-12

申请号：US18651436

申请日：2024-04-30

Applicant: Intel Corporation

Inventor： Laurent CARIOU ,  Thomas J. KENNEY

IPC: H04W8/02 ,  H04W36/08

CPC classification number: H04W8/02 ,  H04W36/08

Abstract: This disclosure describes systems, methods, and devices related to enhanced BSS roaming. A device may generate a basic service set transition management (BTM) query frame comprising one or more fields. The device may include an indication of an intent to receive information from an associated AP, wherein the information is related to preserving one or more agreements with a target neighbor AP recommended by the associated AP. The device may cause to send the frame to the AP. The device may identify a BTM request frame received from the associated AP.