公开(公告)号：US20240305533A1

公开(公告)日：2024-09-12

申请号：US18550387

申请日：2022-06-30

Applicant: Intel Corporation

Inventor： Jingwen BAI ,  Shu-ping YEH ,  Shilpa TALWAR

IPC: H04L41/0895 ,  H04L41/5009 ,  H04W24/08 ,  H04W72/11 ,  H04W72/115

CPC classification number: H04L41/0895 ,  H04L41/5009 ,  H04W24/08 ,  H04W72/11 ,  H04W72/115

Abstract: The present disclosure provides a resilient (radio) access network ((R)AN) slicing framework encompassing a resource planning engine and distributed dynamic slice-aware scheduling modules at one or more network access nodes, edge compute nodes, or cloud computing service. The resilient (R)AN slicing framework includes resource planning and slice-aware scheduling, as well as signaling exchanges for provisioning resilient (R)AN slicing. The intelligent (R)AN slicing framework can realize resource isolation in a more efficient and agile manner than existing network slicing technologies.

公开(公告)号：US20240304549A1

公开(公告)日：2024-09-12

申请号：US18668042

申请日：2024-05-17

Applicant: Intel Corporation

Inventor： Hui Jae Yoo ,  Kevin L. Lin

IPC: H01L23/528 ,  H01L21/311 ,  H01L21/32 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/31116 ,  H01L21/32 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5286 ,  H01L23/53228

Abstract: Integrated circuit metallization lines having a planar top surface but different vertical heights, for example to control intra-layer resistance/capacitance of integrated circuit interconnect. A hardmask material layer may be inserted between two thicknesses of dielectric material that are over a via metallization. Following deposition of the hardmask material layer, trench openings may be patterned through the hardmask layer to define where line metallization will have a greater height. Following the deposition of a thickness of dielectric material over the hardmask material layer, a trench pattern may be etched through the uppermost thickness of dielectric material, exposing the hardmask material layer wherever the trench does not coincide with an opening in the hardmask material layer. The trench etch may be retarded where the hardmask material layer is exposed, resulting to trenches of differing depth. Trenches of differing depth may be filled with metallization and then planarized.

公开(公告)号：US20240303793A1

公开(公告)日：2024-09-12

申请号：US18615667

申请日：2024-03-25

Applicant: Intel Corporation

Inventor： Dmitry Grilikhes

IPC: G06T5/92 ,  G06T5/40 ,  G06V10/60

CPC classification number: G06T5/92 ,  G06T5/40 ,  G06V10/60

Abstract: Techniques for improving image quality of a HDR image by increasing the contrast in the dark portion of the image while preserving the bright parts of the image. The methods preserve the input dynamic range. An image with a luminance histogram gap between a main portion with low brightness and a small portion with high brightness. A first tone mapping curve is determined for the low brightness portion of the image. A second tone mapping curve is determined from a selected point on the first tone mapping curve to a maximum brightness level of the input image. A final tone mapping curve is generated including the first tone mapping curve from a minimum brightness input to the selected point and the second tone mapping curve from the selected point to a maximum brightness level. The method can increase overall image quality and contrast.

公开(公告)号：US12089117B2

公开(公告)日：2024-09-10

申请号：US17500155

申请日：2021-10-13

Applicant: Intel Corporation

Inventor： Ralf Graefe ,  Florian Geissler ,  Rainer Makowitz

IPC: H04W4/06 ,  G05D1/00 ,  G08G1/09 ,  H04W4/38 ,  H04W4/40 ,  H04W4/46 ,  H04W84/18

CPC classification number: H04W4/06 ,  G05D1/028 ,  G08G1/091 ,  H04W4/38 ,  H04W4/40 ,  H04W4/46 ,  G05D1/0088 ,  H04W84/18

Abstract: Systems, methods, and computer-readable media are provided for wireless sensor networks (WSNs), including vehicle-based WSNs. A road side unit (RSU) includes one or more fixed sensors covering different sectors of a designated coverage area. The RSU uses the sensors to capture sensor data that is representative of objects in the coverage area, tracks objects (e.g., vehicles) in the coverage area, and determines regions in the coverage area that are not adequately covered by the sensors (e.g., “perception gaps”). When the RSU identifies an object that is in or at a perception gap, then the RSU sends a request to that object for sensor data captured by the object's on-board sensors. The RSU obtains the sensor data from the object, and uses the obtained sensor data to complement the knowledge that the RSU (i.e., “filling the perception gaps”). Other embodiments are disclosed and/or claimed.

公开(公告)号：US12088329B2

公开(公告)日：2024-09-10

申请号：US17131866

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Mehnaz Rahman ,  Oner Orhan ,  Hosein Nikopour

IPC: H04B1/00 ,  H04B1/04

CPC classification number: H04B1/0057 ,  H04B1/0067 ,  H04B1/0483 ,  H04B2001/0491

Abstract: A transmitter for chip to chip communication may include a modulator and a transmit frequency converter. The modulator may modulate a first received signal according to a first modulation scheme. The modulator may also modulate a second received signal according to a second modulation scheme. The transmit frequency converter may center the first received signal on a first frequency that does not comprise a phase within a radio frequency (RF) domain to generate a first centered signal. The transmit frequency converter may also center the second received signal on a second frequency that comprises a phase within the frequency band to generate a second centered signal. The second centered signal may be orthogonal to the first centered signal. A frequency gap may be positioned between the first centered signal and the second centered signal within the frequency band.

公开(公告)号：US12088060B2

公开(公告)日：2024-09-10

申请号：US17074050

申请日：2020-10-19

Applicant: Intel Corporation

Inventor： Karan Mehta ,  Richard Jones ,  Ranjeet Kumar ,  Guan-Lin Su ,  Duanni Huang ,  Haisheng Rong

IPC: H01S5/068 ,  H01S5/065 ,  H01S5/125 ,  H01S5/30

CPC classification number: H01S5/068 ,  H01S5/0651 ,  H01S5/06821 ,  H01S5/125 ,  H01S5/3013

Abstract: Embodiments of the present disclosure are directed to multi-wavelength laser generator may produce light with a frequency comb having equally spaced frequency lines. In various embodiments, the laser generator includes first, a semiconductor gain element is used to provide gain to the laser being generated. Second, a ring resonator filter, or ring filter, is used to select the wavelength comb spacing. Third, a narrow-band DBR or narrow-band mirror is used to select the number of wavelengths that lase. Fourth, a wide-band or narrow-band mirror is used to provide optical feedback and to form the optical cavity. Fifth, a phase tuner section is used to align the cavity modes with the ring resonances (i.e. the ring filter modes) in order to reduce or minimize the modal loss. Other embodiments may be described and/or claimed.

公开(公告)号：US12087995B2

公开(公告)日：2024-09-10

申请号：US17455928

申请日：2021-11-22

Applicant: Intel Corporation

Inventor： Jayprakash Thakur ,  Prasanna Pichumani ,  Maruti Tamrakar ,  Doddi Raghavendra ,  Sagar Gupta

IPC: H01Q1/02 ,  H01Q1/12 ,  H01Q9/04

CPC classification number: H01Q1/02 ,  H01Q1/12 ,  H01Q9/04 ,  H01Q9/0407

Abstract: Examples relate to concepts for antenna arrangement and particular to an antenna for an electronic device. An electronic device comprises, a case, a lid and a heat spreading structure. Further, an electronic device comprises a hinge arrangement between the case and the lid. The hinge arrangement comprises at least one hinge structure connecting the lid to the case. Further, the electronic device comprises an antenna. The antenna is arranged in an area of the hinge arrangement. The heat spreading structure extends from the case through the area of the hinge arrangement to the lid.

公开(公告)号：US12086995B2

公开(公告)日：2024-09-10

申请号：US17011647

申请日：2020-09-03

Applicant: Intel Corporation

Inventor： Itay Benou ,  Yevgeny Priziment ,  Tzachi Herskovich

IPC: G06T7/194 ,  G06T7/254 ,  G06V10/44 ,  G06V10/80 ,  G06V20/40

CPC classification number: G06T7/254 ,  G06T7/194 ,  G06V10/454 ,  G06V10/803 ,  G06V20/46 ,  G06T2207/10016 ,  G06T2207/20084 ,  G06T2207/20221

Abstract: Techniques related to video background estimation inclusive of generating a final background picture absent foreground objects based on input video are discussed. Such techniques include generating first and second estimated background pictures using temporal and spatial background picture modeling, respectively, and fusing the first and second estimated background pictures based on first and second confidence maps corresponding to the first and second estimated background pictures to generate the final estimated background picture.

公开(公告)号：US12086595B2

公开(公告)日：2024-09-10

申请号：US17214853

申请日：2021-03-27

Applicant: Intel Corporation

Inventor： Menachem Adelman ,  Robert Valentine ,  Amit Gradstein ,  Daniel Towner ,  Mark Charney

IPC: G06F9/30

CPC classification number: G06F9/3016 ,  G06F9/30025 ,  G06F9/30098

Abstract: Systems, methods, and apparatuses relating to interleaving data values. An embodiment includes decoding circuitry to decode a single instruction, the instruction having one or more fields to specify an opcode, one or more fields to specify a location of a first source operand, one or more fields to specify a location of a second source operand, one or more fields to specify a location of a destination operand, and one or more fields to specify an index value to be used to index a row in the first source operand, wherein the opcode is to indicate execution circuitry is to downconvert data elements of the indexed row of the first source operand, interleave the downconverted elements with data elements of the second source operand, and store the interleaved elements in the destination operand; and execution circuitry to execute the decoded instruction according to the opcode.

公开(公告)号：US12086591B2

公开(公告)日：2024-09-10

申请号：US17214698

申请日：2021-03-26

Applicant: Intel Corporation

Inventor： Sudhanshu Shukla ,  Jayesh Gaur ,  Stanislav Shwartsman ,  Pavel I. Kryukov

IPC: G06F9/22 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/3856

Abstract: Techniques and mechanisms for determining a relative order in which a load instruction and a store instruction are to be executed. In an embodiment, a processor detects an address collision event wherein two instructions, corresponding to different respective instruction pointer values, target the same memory address. Based on the address collision event, the processor identifies respective instruction types of the two instructions as an aliasing instruction type pair. The processor further determines a count of decisions each to forego a reversal of an order of execution of instructions. Each decision represented in the count is based on instructions which are each of a different respective instruction type of the aliasing instruction type pair. In another embodiment, the processor determines, based on the count of decisions, whether a later load instruction is to be advanced in an order of instruction execution.