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    Compression for sparse data structures utilizing mode search approximation
    531.
    发明授权
    Compression for sparse data structures utilizing mode search approximation 有权

    公开(公告)号：US12086120B2

    公开(公告)日：2024-09-10

    申请号：US18066436

    申请日：2022-12-15

    Applicant: Intel Corporation

    Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Karol Szerszen ,  Eric Liskay ,  Karthik Vaidyanathan

    IPC: G06F16/22 ,  G06N20/00 ,  G06T1/20

    CPC classification number: G06F16/2237 ,  G06N20/00 ,  G06T1/20

    Abstract: Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.

    Apparatuses, methods, and systems for a configurable accelerator having dataflow execution circuits
    532.
    发明授权
    Apparatuses, methods, and systems for a configurable accelerator having dataflow execution circuits 有权

    公开(公告)号：US12086080B2

    公开(公告)日：2024-09-10

    申请号：US17033728

    申请日：2020-09-26

    Applicant: Intel Corporation

    Inventor： George Chrysos ,  Bhargavi Narayanasetty ,  Jesus Corbal ,  Ching-Kai Liang ,  Chinmay Ashok ,  Francis Tseng

    IPC: G06F13/16 ,  G06F13/40

    CPC classification number: G06F13/1668 ,  G06F13/4027

    Abstract: Systems, methods, and apparatuses relating to a configurable accelerator having dataflow execution circuits are described. In one embodiment, a hardware accelerator includes a plurality of dataflow execution circuits that each comprise a register file, a plurality of execution circuits, and a graph station circuit comprising a plurality of dataflow operation entries that each include a respective ready field that indicates when an input operand for a dataflow operation is available in the register file, and the graph station circuit is to select for execution a first dataflow operation entry when its input operands are available, and clear ready fields of the input operands in the first dataflow operation entry when a result of the execution is stored in the register file; a cross dependence network coupled between the plurality of dataflow execution circuits to send data between the plurality of dataflow execution circuits according to a second dataflow operation entry; and a memory execution interface coupled between the plurality of dataflow execution circuits and a cache bank to send data between the plurality of dataflow execution circuits and the cache bank according to a third dataflow operation entry.

    PHASE CURRENT BALANCE ARCHITECTURE FOR A MULTI-PHASE POWER CONVERTER
    534.
    发明公开
    PHASE CURRENT BALANCE ARCHITECTURE FOR A MULTI-PHASE POWER CONVERTER 审中-公开

    公开(公告)号：US20240297586A1

    公开(公告)日：2024-09-05

    申请号：US18177426

    申请日：2023-03-02

    Applicant: Intel Corporation

    Inventor： Keng Chen ,  Shunjiang Xu ,  Christopher Schaef ,  Tamir Salus ,  Kishan Joshi ,  Arvind Raghavan ,  Huanhuan Zhang

    IPC: H02M3/158 ,  G06F1/26

    CPC classification number: H02M3/1584 ,  G06F1/26

    Abstract: Embodiments described herein may include apparatus, systems, techniques, and/or processes that are directed to multiphase power converters and how current level outputs of each phase circuit are calibrated. The multiple phase circuits are grouped into multiple subsets, wherein one phase circuit of each subset is designated as a reference phase circuit. The reference phase circuits of each subset are calibrated together, using, for example, a closed loop daisy chain technique where each reference phase circuit calibrates their current output to the current output of the previous phase circuit, or alternatively, a current averaging technique where each reference phase circuit balances their current output to the average output of the reference phase circuits. The other phase circuits in each subset calibrate their current level outputs to the reference phase circuits in their subset using, for example, an open loop daisy chain technique, a reference/follower technique or by calibrating their output to the average output of the reference phase circuits.

    TRAINING VIDEO SEGMENTATION MODELS USING TEMPORAL CONSISTENCY LOSS
    535.
    发明公开
    TRAINING VIDEO SEGMENTATION MODELS USING TEMPORAL CONSISTENCY LOSS 审中-公开

    公开(公告)号：US20240296665A1

    公开(公告)日：2024-09-05

    申请号：US18663296

    申请日：2024-05-14

    Applicant: Intel Corporation

    Inventor： Ido Nissenboim ,  Noam Levy ,  Alexander Itskovich

    IPC: G06V10/776 ,  G06V10/764 ,  G06V10/82 ,  G06V20/40

    CPC classification number: G06V10/776 ,  G06V10/764 ,  G06V10/82 ,  G06V20/49

    Abstract: Video segmentation predictions can be temporally unstable. Some techniques can be implemented to mitigate temporal instability, but the techniques can be computationally complex. Some techniques only account for changes in the output and do not account for changes in the input. To address some of these shortcomings, a lightweight technique can be implemented to compute a temporal consistency loss. The temporal consistency loss can be higher when a pixel-wise intensity change is small, and a pixel-wise prediction change is large. The temporal consistency loss can be lower otherwise. The temporal consistency loss can be used with one or more other losses as a part of a loss function for training a segmentation network to improve temporal stability in output segmentation maps.

    TEMPORALLY AMORTIZED SUPERSAMPLING USING A KERNEL SPLATTING NETWORK
    536.
    发明公开
    TEMPORALLY AMORTIZED SUPERSAMPLING USING A KERNEL SPLATTING NETWORK 审中-公开

    公开(公告)号：US20240296605A1

    公开(公告)日：2024-09-05

    申请号：US18566218

    申请日：2021-11-03

    Applicant: Intel Corporation

    Inventor： Dmitry Kozlov ,  Aleksei Chernigin ,  Dmitry Tarakanov

    IPC: G06T11/40 ,  G06T3/4046

    CPC classification number: G06T11/40 ,  G06T3/4046 ,  G06T2210/52

    Abstract: One embodiment provides a graphics processor comprising a set of processing resources configured to perform a supersampling anti-aliasing operation via a mixed precision convolutional neural network. The set of processing resources include circuitry configured to receive, at an input block of a neural network model, a set of data including previous frame data, current frame data, jitter offset data, and velocity data, pre-process the set of data to generate pre-processed data, provide pre-processed data to a feature extraction network of the neural network model and an output block of the neural network model, process the first pre-processed data at the feature extraction network via one or more encoder stages and one or more decoder stages, output tensor data from the feature extraction network to the output block, and generate an anti-aliased output frame via the output block based on the current frame data and the tensor data output from the feature extraction network.

    HUMAN-COLLABORATIVE ROBOT ERGONOMIC INTERACTION SYSTEM
    539.
    发明公开
    HUMAN-COLLABORATIVE ROBOT ERGONOMIC INTERACTION SYSTEM 审中-公开

    公开(公告)号：US20240293931A1

    公开(公告)日：2024-09-05

    申请号：US18397441

    申请日：2023-12-27

    Applicant: Intel Corporation

    Inventor： Javier Turek ,  Leobardo Campos Macias ,  Rafael De La Guardia Gonzalez ,  Javier Felip Leon ,  David Gonzalez Aguirre

    IPC: B25J9/16

    CPC classification number: B25J9/161 ,  B25J9/1661 ,  B25J9/1664 ,  B25J9/1669

    Abstract: A system for human-cobot (collaborative robot) ergonomic interaction, including: a communication interface operable to receive sensor data related to human motion; ergonomic assessment processor circuitry operable to evaluate the sensor data to generate a strain score for at least one human joint, wherein the strain score represents a strain level of the at least one human joint based on an integration of motion of the at least one human joint over a period of time; human intent prediction processor circuitry operable to interpret the sensor data to predict an object the human intends to grasp, and to select a destination container for the predicted object; and cobot motion processor circuitry operable to determine a position or orientation for the cobot to place the selected destination container based on the predicted object and the strain score.

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