公开(公告)号：US11362218B2

公开(公告)日：2022-06-14

申请号：US16910022

申请日：2020-06-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Elizabeth Cuevas ,  Yuri Tkachev ,  Parviz Ghazavi ,  Bernard Bertello ,  Gilles Festes ,  Bruno Villard ,  Catherine Decobert ,  Nhan Do ,  Jean Francois Thiery

IPC: H01L27/11517 ,  H01L27/11531 ,  H01L29/788 ,  H01L29/66 ,  H01L27/11543 ,  H01L27/11551 ,  H01L27/11524 ,  H01L27/11521 ,  H01L27/11529 ,  H01L27/11534

Abstract: A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.

公开(公告)号：US11362100B2

公开(公告)日：2022-06-14

申请号：US17069563

申请日：2020-10-13

Applicant: Silicon Storage Technology, Inc.

Inventor： Feng Zhou ,  Xian Liu ,  Steven Lemke ,  Hieu Van Tran ,  Nhan Do

IPC: H01L27/11517 ,  H01L27/11529 ,  H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11551

Abstract: Memory cells formed on upwardly extending fins of a semiconductor substrate, each including source and drain regions with a channel region therebetween, a floating gate extending along the channel region and wrapping around the fin, a word line gate extending along the channel region and wrapping around the fin, a control gate over the floating gate, and an erase gate over the source region. The control gates are a continuous conductive strip of material. First and second fins are spaced apart by a first distance. Third and fourth fins are spaced apart by a second distance. The second and third fins are spaced apart by a third distance greater than the first and second distances. The continuous strip includes a portion disposed between the second and third fins, but no portion of the continuous strip is disposed between the first and second fins nor between the third and fourth fins.

公开(公告)号：US11354562B2

公开(公告)日：2022-06-07

申请号：US15936983

申请日：2018-03-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Anh Ly ,  Thuan Vu ,  Hien Pham ,  Kha Nguyen ,  Han Tran

IPC: G06N3/04 ,  G06F17/16 ,  G06N3/063 ,  G06N3/08 ,  G11C16/04 ,  G11C11/54 ,  H03F3/45

Abstract: Numerous embodiments for processing the current output of a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The embodiments comprise a summer circuit and an activation function circuit. The summer circuit and/or the activation function circuit comprise circuit elements that can be adjusted in response to the total possible current received from the VMM to optimize power consumption.

公开(公告)号：US11322507B2

公开(公告)日：2022-05-03

申请号：US17185709

申请日：2021-02-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Jack Sun ,  Xian Liu ,  Leo Xing ,  Nhan Do ,  Andy Yang ,  Guo Xiang Song

IPC: H01L21/00 ,  H01L27/11531 ,  H01L27/11521 ,  H01L29/788 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49

Abstract: A method of forming a semiconductor device includes recessing the upper surface of first and second areas of a semiconductor substrate relative to the third area of the substrate, forming a pair of stack structures in the first area each having a control gate over a floating gate, forming a first source region in the substrate between the pair of stack structures, forming an erase gate over the first source region, forming a block of dummy material in the third area, forming select gates adjacent the stack structures, forming high voltage gates in the second area, forming a first blocking layer over at least a portion of one of the high voltage gates, forming silicide on a top surface of the high voltage gates which are not underneath the first blocking layer, and replacing the block of dummy material with a block of metal material.

公开(公告)号：US11315940B2

公开(公告)日：2022-04-26

申请号：US17151944

申请日：2021-01-19

Applicant: Silicon Storage Technology, Inc.

Inventor： Chunming Wang ,  Guo Xiang Song ,  Leo Xing ,  Jack Sun ,  Xian Liu ,  Nhan Do

IPC: H01L27/11531 ,  H01L27/11521 ,  H01L29/78 ,  H01L21/762 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/265 ,  H01L29/788

Abstract: A method of forming memory cells, HV devices and logic devices on a substrate, including recessing the upper surface of the memory cell and HV device areas of the substrate, forming a polysilicon layer in the memory cell and HV device areas, forming first trenches through the first polysilicon layer and into the silicon substrate in the memory cell and HV device areas, filling the first trenches with insulation material, forming second trenches into the substrate in the logic device area to form upwardly extending fins, removing portions of the polysilicon layer in the memory cell area to form floating gates, forming erase and word line gates in the memory cell area, HV gates in the HV device area, and dummy gates in the logic device area from a second polysilicon layer, and replacing the dummy gates with metal gates that wrap around the fins.

公开(公告)号：US11309042B2

公开(公告)日：2022-04-19

申请号：US16915289

申请日：2020-06-29

Applicant: Silicon Storage Technology, Inc.

Inventor： Viktor Markov ,  Alexander Kotov

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/14 ,  G11C16/26 ,  G11C16/10 ,  G11C16/04

Abstract: A method and device for programming a non-volatile memory cell, where the non-volatile memory cell includes a first gate. The non-volatile memory cell is programmed to an initial program state that corresponds to meeting or exceeding a target threshold voltage for the first gate of the non-volatile memory cell. The target threshold voltage corresponds to a target read current. The non-volatile memory cell is read in a first read operation using a read voltage applied to the first gate of the non-volatile memory cell that is less than the target threshold voltage to generate a first read current. The non-volatile memory cell is subjected to additional programming in response to determining that the first read current is greater than the target read current.

公开(公告)号：US20210399127A1

公开(公告)日：2021-12-23

申请号：US16910022

申请日：2020-06-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Jinho Kim ,  Elizabeth Cuevas ,  Yuri Tkachev ,  Parviz Ghazavi ,  Bernard Bertello ,  Gilles Festes ,  Bruno Villard ,  Catherine Decobert ,  Nhan Do ,  Jean Francois Thiery

IPC: H01L29/788 ,  H01L29/66 ,  H01L27/11517

Abstract: A memory device includes a semiconductor substrate with memory cell and logic regions. A floating gate is disposed over the memory cell region and has an upper surface terminating in opposing front and back edges and opposing first and second side edges. An oxide layer has a first portion extending along the logic region and a first thickness, a second portion extending along the memory cell region and has the first thickness, and a third portion extending along the front edge with the first thickness and extending along a tunnel region portion of the first side edge with a second thickness less than the first thickness. A control gate has a first portion disposed on the oxide layer second portion and a second portion vertically over the front edge and the tunnel region portion of the first side edge. A logic gate is disposed on the oxide layer first portion.

公开(公告)号：US11158374B2

公开(公告)日：2021-10-26

申请号：US16930777

申请日：2020-07-16

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Steven Lemke ,  Nhan Do ,  Vipin Tiwari ,  Mark Reiten

IPC: G11C16/04 ,  G06F17/16 ,  G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: Numerous embodiments are disclosed for providing temperature compensation in a an analog memory array. The analog memory array optionally is a vector-by-matrix multiplier in an analog neuromorphic memory system used in a deep learning neural network. One embodiment comprises measuring an operating temperature within a memory array and applying, by a temperature compensation block, a bias voltage to a terminal of a memory cell in the array, wherein the bias voltage is a function of the operating temperature.

公开(公告)号：US20210280239A1

公开(公告)日：2021-09-09

申请号：US16986812

申请日：2020-08-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan VU ,  Stephen TRINH ,  Stanley HONG ,  Anh LY ,  Vipin Tiwari

IPC: G11C11/54 ,  G11C16/04 ,  G11C16/26 ,  G06N3/063

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In certain embodiments, each memory cell in the array has an approximately constant source impedance when that cell is being operated. In certain embodiments, power consumption is substantially constant from bit line to bit line within the array when cells are being read. In certain embodiments, weight mapping is performed adaptively for optimal performance in power and noise.

公开(公告)号：US20210210144A9

公开(公告)日：2021-07-08

申请号：US16574059

申请日：2019-09-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/12 ,  G11C16/04 ,  G11C16/24

Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed. In one embodiment, a programming circuit comprises a switch configured to couple a current source to a capacitor during a first mode and to uncouple the current source from the capacitor during the second mode, wherein during the second mode the capacitor is coupled to the gate of a transistor used to program a memory cell.