公开(公告)号：US20160071598A1

公开(公告)日：2016-03-10

申请号：US14810283

申请日：2015-07-27

Applicant: STMicroelectronics ( Rousset ) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/26

Abstract: A method controls a memory that includes twin memory cells formed in a semiconductor substrate. Each memory cell includes a floating-gate transistor including a state control gate, in series with a select transistor that includes a vertical select control gate, common to the twin memory cells, and a source connected to an embedded source line, common to the memory cells. The drains of the floating-gate transistors of the twin memory cells are connected to a same bit line. The method includes controlling a memory cell so as to turn it on to couple the source line to a bit line coupled to the ground, during a step of programming or reading another memory cell.

Abstract translation: 一种方法控制包括形成在半导体衬底中的双存储单元的存储器。 每个存储单元包括一个浮动栅极晶体管，它包括状态控制栅极，与选择晶体管串联，该选择​​晶体管包括双存储单元共用的垂直选择控制栅极和连接到存储器共用的嵌入式源极线路的源极 细胞。 双存储单元的浮栅晶体管的漏极连接到相同的位线。 该方法包括在编程或读取另一个存储器单元的步骤期间控制存储器单元以将其导通以将源极线耦合到耦合到地的位线。

公开(公告)号：US09277577B2

公开(公告)日：2016-03-01

申请号：US14176959

申请日：2014-02-10

Applicant: Proton World International N.V. ,  STMicroelectronics (Rousset) SAS

Inventor： Olivier Van Nieuwenhuyze ,  Alexandre Charles

IPC: H04W64/00 ,  H04W76/02 ,  H04W4/00 ,  H04B5/00 ,  H04B5/02

CPC classification number: H04L41/0803 ,  H04B5/0031 ,  H04B5/02 ,  H04L67/104 ,  H04W4/80 ,  H04W76/14

Abstract: A method for configuring a first device for a near-field communication with a second device, wherein a peer-to-peer mode is selected if the second device draws the power supply of its circuits from a battery.

Abstract translation: 一种用于配置用于与第二设备进行近场通信的第一设备的方法，其中如果所述第二设备从电池抽取其电路的电源，则选择对等模式。

公开(公告)号：US20160056364A1

公开(公告)日：2016-02-25

申请号：US14930204

申请日：2015-11-02

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L35/32 ,  H01L23/522 ,  H01L27/16 ,  H01L23/528

CPC classification number: H01L35/32 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated thermoelectric generator includes a semiconductor. A set of thermocouples are electrically connected in series and thermally connected in parallel. The set of thermocouples include parallel semiconductor regions. Each semiconductor region has one type of conductivity from among two opposite types of conductivity. The semiconductor regions are electrically connected in series so as to form a chain of regions having, alternatingly, one and the other of the two types of conductivity.

公开(公告)号：US09245624B2

公开(公告)日：2016-01-26

申请号：US14298264

申请日：2014-06-06

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista

IPC: G11C14/00 ,  G11C16/10

CPC classification number: G11C14/0063 ,  G11C16/10

Abstract: A memory device includes at least one memory cell having a first SRAM-type elementary memory cell having two inverters coupled to one another crosswise and two groups, each having at least one non-volatile elementary memory cell. The non-volatile elementary memory cells of the two groups are coupled firstly to a supply terminal and secondly to the outputs and to the inputs of the two inverters via a controllable interconnection stage.

Abstract translation: 存储器件包括至少一个具有第一SRAM型元件存储器单元的存储器单元，所述第一SRAM型元件存储器单元具有彼此交叉耦合的两个反相器和两组，每个具有至少一个非易失性基本存储器单元。 两组的非易失性基本存储单元首先通过可控制的互连级耦合到电源端子，其次耦合到两个反相器的输出端和输入端。

公开(公告)号：US09230907B2

公开(公告)日：2016-01-05

申请号：US14264227

申请日：2014-04-29

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L21/02 ,  H01L23/522 ,  H01L21/768 ,  H01G5/16 ,  H01L23/64

CPC classification number: H01L27/0629 ,  H01G5/011 ,  H01G5/16 ,  H01L21/768 ,  H01L21/7682 ,  H01L21/7687 ,  H01L23/4821 ,  H01L23/5223 ,  H01L23/528 ,  H01L23/642 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2924/00

Abstract: An integrated circuit includes a substrate. A fixed main capacitor electrode is disposed in a metal layer overlying the substrate. A second main capacitor electrode is disposed in a metal layer and spaced from the fixed main capacitor electrode. A movable capacitor electrode is disposed adjacent the fixed main capacitor electrode. The movable capacitor electrode is switchable between a first configuration in which the movable capacitor electrode and fixed main capacitor electrode are mutually spaced out in such a manner as to form an auxiliary capacitor electrically connected to the main capacitor. In a second configuration, the movable capacitor electrode and the fixed main capacitor electrode are in electrical contact in such a manner as to give a second capacitive value.

Abstract translation: 集成电路包括基板。 固定的主电容器电极设置在覆盖衬底的金属层中。 第二主电容器电极设置在金属层中并与固定主电容器电极间隔开。 可动电容电极设置在固定主电容器电极附近。 可移动电容器电极可以在可移动电容器电极和固定主电容器电极相互间隔开的第一配置之间切换，以形成电连接到主电容器的辅助电容器。 在第二构造中，可移动电容电极和固定主电容器电极以提供第二电容值的方式进行电接触。

公开(公告)号：US20150372155A1

公开(公告)日：2015-12-24

申请号：US14675468

申请日：2015-03-31

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pascal Fornara ,  Christian Rivero

IPC: H01L29/93 ,  H01L23/04 ,  H01L23/528 ,  H01L23/532 ,  H01L23/522 ,  H01L27/06

CPC classification number: H01L23/04 ,  B81B3/0021 ,  B81B2201/0221 ,  H01G5/18 ,  H01L23/5223 ,  H01L27/0629 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit includes several metallization levels separated by an insulating region. A hollow housing whose walls comprise metallic portions is produced within various metallization levels. A controllable capacitive device includes a suspended metallic structure situated in the hollow housing within a first metallization level including a first element fixed on two fixing zones of the housing and at least one second element extending in cantilever fashion from the first element and includes a first electrode of the capacitive device. A second electrode includes a first fixed body situated at a second metallization level adjacent to the first metallization level facing the first electrode. The first element is controllable in flexion from a control zone of this first element so as to modify the distance between the two electrodes.

Abstract translation: 集成电路包括由绝缘区隔开的几个金属化层。 在各种金属化水平下产生其壁包括金属部分的中空壳体。 可控电容器件包括位于第一金属化水平的中空壳体内的悬挂金属结构，该第一金属化水平包括固定在壳体的两个固定区域上的第一元件和从第一元件以悬臂方式延伸的至少一个第二元件，并且包括第一电极 的电容器件。 第二电极包括位于与面向第一电极的第一金属化水平相邻的第二金属化水平的第一固定体。 第一元件可以从该第一元件的控制区域的弯曲中控制，以便改变两个电极之间的距离。

公开(公告)号：US20150356300A1

公开(公告)日：2015-12-10

申请号：US14668692

申请日：2015-03-25

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Yannick Teglia

IPC: G06F21/57 ,  G06F12/14

CPC classification number: G06F21/575 ,  G01K13/00 ,  G06F12/1458 ,  G06F21/554 ,  G06F21/71 ,  G06F2212/1052 ,  G06F2221/034 ,  G06F2221/2137

Abstract: A method of detecting a cold-boot attack on an integrated circuit including the steps of: transferring, into a first volatile memory of the integrated circuit, a pattern stored in a non-volatile memory of the circuit; periodically causing a switching down and a switching up of the first volatile memory; and verifying that the number of bits having switched state is within a range of values.

Abstract translation: 一种检测集成电路的冷启动攻击的方法，包括以下步骤：向集成电路的第一易失性存储器传送存储在电路的非易失性存储器中的模式; 周期性地引起第一易失性存储器的切换和切换; 以及验证具有切换状态的位数在值的范围内。

公开(公告)号：US20150348635A1

公开(公告)日：2015-12-03

申请号：US14719913

申请日：2015-05-22

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Stephan Niel ,  Arnaud Regnier

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/14 ,  G11C16/0408 ,  G11C16/0425 ,  G11C16/0458 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11517

Abstract: The present disclosure relates to a method for controlling two twin memory cells each comprising a floating-gate transistor comprising a state control gate, in series with a select transistor comprising a select control gate common to the two memory cells, the drains of the floating-gate transistors being connected to a same bit line, the method comprising steps of programming the first memory cell by hot-electron injection, by applying a positive voltage to the bit line and a positive voltage to the state control gate of the first memory cell, and simultaneously, of applying to the state control gate of the second memory cell a positive voltage capable of causing a programming current to pass through the second memory cell, without switching it to a programmed state.

Abstract translation: 本公开涉及一种用于控制两个双存储单元的方法，每个双存储器单元包括浮置晶体管，其包括状态控制栅极，与包括两个存储单元共用的选择控制栅极的选择晶体管串联， 栅极晶体管连接到相同的位线，该方法包括以下步骤：通过对位线施加正电压并将正电压施加到第一存储单元的状态控制栅极，通过热电子注入来对第一存储单元进行编程， 并且同时向第二存储单元的状态控制栅极施加能够使编程电流通过第二存储单元的正电压，而不将其切换到编程状态。

公开(公告)号：US20150340426A1

公开(公告)日：2015-11-26

申请号：US14715814

申请日：2015-05-19

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Sylvie Wuidart ,  Christian Rivero ,  Guilhem Bouton ,  Pascal Fornara

IPC: H01L49/02 ,  H01L27/06 ,  H01L29/423 ,  H01L27/115 ,  H01L29/78

CPC classification number: H01L28/60 ,  H01L27/0629 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/42356 ,  H01L29/66181 ,  H01L29/7842 ,  H01L29/94 ,  H01L29/945

Abstract: An integrated circuit includes a substrate and a circuit component (such as a MOS device or resistance) disposed at least partially within an active region of the substrate limited by an insulating region. A capacitive structure including a first electrode (for connection to a first potential such as ground) and a second electrode (for connection to a second potential such as a supply voltage) is provided in connection with the insulating region. One of the first and second electrodes is situated at least in part within the insulating region. The capacitive structure is thus configured in order to allow a reduction in compressive stresses within the active region.

Abstract translation: 集成电路包括基板和至少部分地设置在由绝缘区域限制的基板的有源区域内的电路部件（诸如MOS器件或电阻）。 结合绝缘区域提供包括第一电极（用于连接到第一电位例如接地）和第二电极（用于连接到第二电位例如电源电压）的电容结构。 第一和第二电极之一至少部分地位于绝缘区域内。 因此，电容结构被配置为允许有效区域内的压缩应力的降低。

公开(公告)号：US20150270002A1

公开(公告)日：2015-09-24

申请号：US14657963

申请日：2015-03-13

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Marc Battista ,  François Tailliet

IPC: G11C16/04 ,  H01L29/49 ,  H01L27/088 ,  H01L29/51 ,  G11C16/08 ,  G11C11/418

CPC classification number: H01L27/1104 ,  G11C11/4125 ,  G11C11/418 ,  G11C14/0063 ,  G11C16/045 ,  G11C16/08 ,  H01L21/823462 ,  H01L27/088 ,  H01L29/4916 ,  H01L29/513

Abstract: An integrated structure includes a first MOS transistor with a first controllable gate region overlying a first gate dielectric and a second MOS transistor neighboring the first MOS transistor and having a second controllable gate region overlying the first gate dielectric. A common conductive region overlies the first and second gate regions and is separated therefrom by a second gate dielectric. The common conductive region includes a continuous element located over a portion of the first and second gate regions and a branch extending downward from the continuous element toward the substrate as far as the first gate dielectric. The branch located between the first and second gate regions.

Abstract translation: 集成结构包括具有覆盖第一栅极电介质的第一可控栅极区域和与第一MOS晶体管相邻并且具有覆盖第一栅极电介质的第二可控栅极区域的第一MOS晶体管的第一MOS晶体管。 公共导电区域覆盖第一和第二栅极区域并且由第二栅极电介质分离。 公共导电区域包括位于第一和第二栅极区域的一部分上的连续元件以及从连续元件向衬底延伸至第一栅极电介质的分支。 位于第一和第二栅极区之间的分支。