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166 条记录 (耗时 0.023 秒)

    Concurrent multi-bit adder
    51.
    发明授权
    Concurrent multi-bit adder 有权

    公开(公告)号：US10402165B2

    公开(公告)日：2019-09-03

    申请号：US15690301

    申请日：2017-08-30

    申请人： GSI Technology Inc.

    发明人： Moshe Lazer

    IPC分类号： G06F7/508 ,  G06F12/02

    摘要： A system includes a non-destructive associative memory array and a predictor, a selector and a summer. The memory array includes a plurality of sections, each section includes cells arranged in rows and columns, to store bit j from a first multi-bit number and bit j from a second multi-bit number in a same column in section j. The predictor generally concurrently predicts a plurality of carry out values in each of the sections and the selector selects one of the predicted carry out values for all bits. The summer generally concurrently, for all bits, calculates a sum of the multi-bit numbers using the selected carry-out values.

    SYSTEMS AND METHODS INVOLVING PSEUDO COMPLEMENTARY OUTPUT BUFFER CIRCUITRY/SCHEMES, POWER NOISE REDUCTION AND/OR OTHER FEATURES
    56.
    发明申请
    SYSTEMS AND METHODS INVOLVING PSEUDO COMPLEMENTARY OUTPUT BUFFER CIRCUITRY/SCHEMES, POWER NOISE REDUCTION AND/OR OTHER FEATURES 有权
    涉及PSEUDO补充输出缓冲器电路/方案，电源噪声减少和/或其他特性的系统和方法

    公开(公告)号：US20170063372A1

    公开(公告)日：2017-03-02

    申请号：US15248985

    申请日：2016-08-26

    申请人： GSI Technology, Inc.

    发明人： Jae-Hyeong KIM ,  Chih TSENG ,  Patrick CHUANG

    IPC分类号： H03K17/687

    CPC分类号： H03K19/0185

    摘要： A system may include a first inverter configured to invert a first data signal and a second inverter configured to invert a second data signal. A pull-up element may be coupled to an output of the first inverter on a first terminal and a power source on a second terminal, wherein the power source is also coupled to a pull-up element of a main output buffer. A pull-down element may b e coupled to an output of the second inverter on a first terminal and a ground on a second terminal, wherein the ground is also coupled to a pull-down element of the main output buffer.

    摘要翻译： 系统可以包括被配置为反转第一数据信号的第一反相器和被配置为反转第二数据信号的第二反相器。 上拉元件可以耦合到第一端子上的第一反相器的输出端和第二端子上的电源，其中电源也耦合到主输出缓冲器的上拉元件。 下拉元件可以耦合到第二端子上的第二反相器的输出端和第二端子上的接地端，其中接地还耦合到主输出缓冲器的下拉元件。

    Systems and methods of phase frequency detection involving features such as improved clock edge handling circuitry/aspects
    57.
    发明授权
    Systems and methods of phase frequency detection involving features such as improved clock edge handling circuitry/aspects 有权

    公开(公告)号：US09509296B1

    公开(公告)日：2016-11-29

    申请号：US14797269

    申请日：2015-07-13

    申请人： GSI TECHNOLOGY, INC.

    发明人： Yu-Chi Cheng

    IPC分类号： H03L7/06 ,  H03K5/1534 ,  H03L7/089 ,  H03L7/091

    CPC分类号： H03K5/1534 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/091

    摘要： Systems and methods herein may include or involve control circuitry that detects missing edges of reference and/or feedback clocks and may block the next N rising edges of the feedback clock or reference clock, respectively. In some implementations, a phase frequency detector (PFD) circuit comprises first circuitry including an output that outputs a missing edge signal. The first circuitry may include components arranged to detect a missing rising edge of one or both of a reference clock signal and a feedback clock signal. Second circuitry is coupled to the first circuitry and may include components arranged to generate one or both of a reference clock blocking signal and a feedback clock blocking signal based on the missing edge signal. Further, in some implementations, the blocking of the next N rising edges of the opposite clock may effectively increase the positive gain of the PFD.

    Systems and methods involving data inversion devices, circuitry, schemes and/or related aspects
    58.
    发明授权
    Systems and methods involving data inversion devices, circuitry, schemes and/or related aspects 有权
    涉及数据反转装置，电路，方案和/或相关方面的系统和方法

    公开(公告)号：US09494647B1

    公开(公告)日：2016-11-15

    申请号：US14588368

    申请日：2014-12-31

    申请人： GSI TECHNOLOGY, INC.

    发明人： Patrick T. Chuang ,  Mu-Hsiang Huang ,  Jae Hyeong Kim

    IPC分类号： G11C7/06 ,  G11C16/26 ,  G11C11/4091 ,  G01R31/317

    CPC分类号： G11C11/4091 ,  G11C7/065 ,  G11C7/067 ,  G11C7/1006 ,  G11C7/1057 ,  G11C7/1084 ,  G11C16/26

    摘要： Systems and methods of data inversion, circuitry, detection and/or schemes are disclosed. According to illustrative implementations, exemplary circuitry may include static detection or detection circuitry such as those involving static current sources to detect a threshold for data inversion, pre-conditioning of detection circuitry, and/or active detection circuitry or schemes. In some implementations, exemplary memory or data inversion circuitry may comprise a transistor array, a bias generator, and a sense amplifier, wherein the transistor array may comprise at least one pair of transistor circuits arranged so that an output of the transistor array is provided as a sum or function of signal/current outputs of at least some of the transistor circuits in the array. As set forth, various systems, methods and circuitry herein may posses only a 3 static gate delay, such that very high speed and/or fast flow-through is achieved.

    摘要翻译： 公开了数据反转，电路，检测和/或方案的系统和方法。 根据说明性实现，示例性电路可以包括静态检测或检测电路，例如涉及用于检测用于数据反转的阈值，检测电路的预处理和/或主动检测电路或方案的静态电流源的静态检测或检测电路。 在一些实现中，示例性存储器或数据反转电路可以包括晶体管阵列，偏置发生器和读出放大器，其中晶体管阵列可以包括至少一对晶体管电路，其布置成使得晶体管阵列的输出被提供为 阵列中的至少一些晶体管电路的信号/电流输出的和或函数。 如上所述，本文中的各种系统，方法和电路可以仅具有3个静态门延迟，使得实现非常高的速度和/或快速流通。

    FUNCTIONAL PROTEIN CLASSIFICATION FOR PANDEMIC RESEARCH
    59.
    发明公开
    FUNCTIONAL PROTEIN CLASSIFICATION FOR PANDEMIC RESEARCH 审中-公开

    公开(公告)号：US20240355426A1

    公开(公告)日：2024-10-24

    申请号：US18759907

    申请日：2024-06-30

    申请人： GSI Technology Inc.

    发明人： Elona EREZ

    IPC分类号： G16B40/20 ,  G06F18/2115 ,  G06F18/2413 ,  G06N3/04 ,  G06N3/08 ,  G16B30/00 ,  G16B50/30

    CPC分类号： G16B40/20 ,  G06F18/2115 ,  G06F18/24147 ,  G06N3/04 ,  G06N3/08 ,  G16B30/00 ,  G16B50/30

    摘要： A protein searcher includes a pre-trained CNN, a feature extractor, a database and a KNN searcher. The pre-trained CNN, trained on a previously classified amino acid database, receives an unidentified amino acid sequence. The feature extractor extracts a feature vector of the unidentified amino acid sequence as a query feature vector. The database stores feature vectors of trained amino acid sequences and of at least one untrained amino acid sequence and stores associated classes of the trained amino acid sequences and associated tags of the at least one untrained amino acid sequence. The KNN searcher finds K feature vectors of the database which are close to the query feature vector and outputs the associated class or tag of each of the K feature vectors.

    Functional protein classification for pandemic research
    60.
    发明授权
    Functional protein classification for pandemic research 有权

    公开(公告)号：US12027238B2

    公开(公告)日：2024-07-02

    申请号：US17490018

    申请日：2021-09-30

    申请人： GSI Technology Inc.

    发明人： Elona Erez

    IPC分类号： G16B40/20 ,  G06F18/2115 ,  G06F18/2413 ,  G06N3/04 ,  G06N3/08 ,  G16B30/00 ,  G16B50/30

    CPC分类号： G16B40/20 ,  G06F18/2115 ,  G06F18/24147 ,  G06N3/04 ,  G06N3/08 ,  G16B30/00 ,  G16B50/30

    摘要： A protein searcher includes a pre-trained CNN, a feature extractor, a database and a KNN searcher. The pre-trained CNN, trained on a previously classified amino acid database, receives an unidentified amino acid sequence. The feature extractor extracts a feature vector of the unidentified amino acid sequence as a query feature vector. The database stores feature vectors of trained amino acid sequences and of at least one untrained amino acid sequence and stores associated classes of the trained amino acid sequences and associated tags of the at least one untrained amino acid sequence. The KNN searcher finds K feature vectors of the database which are close to the query feature vector and outputs the associated class or tag of each of the K feature vectors.