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公开(公告)号：US12032089B2
公开(公告)日：2024-07-09
申请号：US16923916
申请日：2020-07-08
发明人： Paul Meissner , Franz Pernkopf , Johanna Rock , Wolfgang Roth , Mate Andras Toth
IPC分类号： G01S7/295 , G01S7/02 , G01S7/282 , G01S7/41 , G01S13/02 , G06N3/063 , G06N3/08 , G06N3/084 , G06N5/04 , G06N5/046 , G01S7/35 , G01S13/34 , G01S13/44 , G01S13/58 , G01S13/931 , G06N3/045
CPC分类号： G01S7/023 , G01S7/282 , G01S7/295 , G01S7/417 , G01S13/02 , G06N3/063 , G06N3/084 , G06N5/046 , G01S7/352 , G01S7/354 , G01S7/356 , G01S13/343 , G01S13/4454 , G01S13/584 , G01S13/931 , G06N3/045
摘要： A radar device may include a radar receiver to receive a radio frequency (RF) radar signal and generate a digital signal based on the RF radar signal. The digital signal may comprise a plurality of signal segments. The radar device may include a neural network comprising a plurality of layers to process the plurality of signal segments. Each layer of the plurality of layers may have one or more neurons. The plurality of layers may process the plurality of signal segments using weighting factors having values selected from a predetermined set of discrete values. At least one neuron in an output layer of the plurality of layers may provide an output value that indicates whether a respective signal segment or a sample, associated with the at least one neuron, is overlaid with an interfering signal.
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公开(公告)号：US12030450B2
公开(公告)日：2024-07-09
申请号：US17351329
申请日：2021-06-18
IPC分类号： B60R21/0136 , B81B3/00 , B60R21/013
CPC分类号： B60R21/0136 , B81B3/0021 , B60R2021/01302 , B81B2201/0257
摘要： A sensor device includes a sensor which is configured to detect a physical quantity generated by an impact event and to generate first measurement data based on the impact event. The sensor device also includes a MEMS microphone configured to detect sound waves generated by the impact event and to generate second measurement data based on the impact event. The sensor device is configured to provide the first measurement data and the second measurement data to a logic unit. The logic unit is configured to detect the impact event based on a combination of the first measurement data and the second measurement data.
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公开(公告)号：US12027481B2
公开(公告)日：2024-07-02
申请号：US18103204
申请日：2023-01-30
发明人： Petteri Palm , Thorsten Scharf
IPC分类号： H01L23/00 , H01L23/538 , H01L25/04 , H05K1/18 , H05K3/00
CPC分类号： H01L24/06 , H01L23/5389 , H01L24/19 , H01L24/20 , H01L24/83 , H01L25/04 , H05K1/188 , H05K3/007 , H01L2224/04105 , H01L2224/06181 , H01L2224/06182 , H01L2224/12105 , H01L2224/2518 , H01L2224/73267 , H01L2224/8019 , H01L2224/83132 , H01L2224/83192 , H01L2224/83447 , H01L2924/00 , H01L2924/12042 , H01L2924/13055 , H01L2924/13091 , H01L2924/15747 , H05K2203/0152 , H01L2924/15747 , H01L2924/00 , H01L2924/13055 , H01L2924/00 , H01L2924/12042 , H01L2924/00 , H01L2924/13091 , H01L2924/00
摘要： A device includes a first semiconductor chip including a first face, wherein a first contact pad is arranged over the first face. The device further includes a second semiconductor chip including a first face, wherein a first contact pad is arranged over the first face, wherein the first semiconductor chip and the second semiconductor chip are arranged such that the first face of the first semiconductor chip faces in a first direction and the first face of the second semiconductor chip faces in a second direction opposite to the first direction. The first semiconductor chip is located laterally outside of an outline of the second semiconductor chip.
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公开(公告)号：US12027436B2
公开(公告)日：2024-07-02
申请号：US17575038
申请日：2022-01-13
发明人： Angela Kessler , Kok Yau Chua , Josef Hoeglauer , Chiah Chin Lim , Mei Qi Tay
IPC分类号： H01L29/06 , H01L21/52 , H01L23/31 , H01L23/495 , H01L23/538 , H01L31/072 , H01L31/109
CPC分类号： H01L23/3157 , H01L21/52 , H01L23/49541 , H01L23/5384
摘要： A package and method of manufacturing is disclosed. In one example, the package which comprises a carrier with at least one component mounted on the carrier. A clip is arranged above the carrier and having a through hole. At least part of at least one of the at least one component and/or at least part of an electrically conductive connection element electrically connecting the at least one component is at least partially positioned inside the through hole.
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公开(公告)号：US20240213997A1
公开(公告)日：2024-06-27
申请号：US18146641
申请日：2022-12-27
发明人： Dan Ioan Dumitru STOICA , Constantin CRISU , Constantin STROI , Vlad BUICULESCU , Matthias BÖHM , Alessandro CASPANI , Cesare BUFFA , Franz Michael DARRER
IPC分类号： H03M1/34 , G10L21/0232 , H03M1/06
CPC分类号： H03M1/34 , G10L21/0232 , H03M1/0626
摘要： A sensor circuit, having a startup phase and an operation phase, includes: a sensor configured to generate a sensor signal based on a measured property, wherein the sensor signal has a frequency spectrum defined by a first frequency and a second frequency that is greater than the first frequency; a signal processing circuit including an analog-to-digital converter (ADC) configured to convert the sensor signal into a digital sensor signal; and an offset diagnosis circuit. The offset diagnosis circuit includes: a low pass filter having a cutoff frequency less than the first frequency and configured to generate a filtered signal based on the digital sensor signal; an offset register configured to store a startup signal value of the filtered signal during the startup phase; and an offset comparator circuit configured to set a threshold range based on the startup signal value for use during the operation phase.
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公开(公告)号：US20240210522A1
公开(公告)日：2024-06-27
申请号：US18598596
申请日：2024-03-07
发明人： Saverio Trotta , Reinhard-Wolfgang Jungmaier , Dennis Noppeney , Ashutosh Baheti , Ismail Nasr , Jagjit Singh Bal
CPC分类号： G01S7/032 , G01S7/003 , G01S7/006 , G01S13/343 , G01S2013/0245
摘要： In accordance with an embodiment, a method of operating a radar system includes receiving radar configuration data from a host, and receiving a start command from the host after receiving the radar configuration data. The radar configuration data includes chirp parameters and frame sequence settings. After receiving the start command, configuring a frequency generation circuit is configured with the chirp parameters and radar frames are triggered at a preselected rate.
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公开(公告)号：US12021139B2
公开(公告)日：2024-06-25
申请号：US17121008
申请日：2020-12-14
发明人： Adrian Finney , Norbert Krischke , Mathias Racki
CPC分类号： H01L29/7803 , G01K7/01 , H01L27/0623 , H01L29/66272 , H01L29/7304 , H01L29/732
摘要： A semiconductor arrangement is disclosed. The semiconductor arrangement includes: a semiconductor body and a temperature sensor (TES) integrated in the semiconductor body. The TES includes: a first semiconductor region of a first doping type arranged, in a vertical direction of the semiconductor body, between a second semiconductor region of a second doping type and a third semiconductor of the second doping type, and a contact plug ohmically connecting the first semiconductor region and the second semiconductor region. The first semiconductor region includes a base region section spaced apart from the contact plug in a first lateral direction of the semiconductor body and a resistor section arranged between the base region section and the contact plug. The resistor section is implemented such that an ohmic resistance of the resistor section between the base region section and the first semiconductor region is at least 1 MΩ.
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公开(公告)号：US12019765B2
公开(公告)日：2024-06-25
申请号：US17548626
申请日：2021-12-13
发明人： Erich Wenger
CPC分类号： G06F21/602 , G06F7/5443
摘要： According to an embodiment, a cryptographic processing device is described comprising a memory configured to store a first operand and a second operand and a cryptographic processor configured to determine, for cryptographically processing the data, the product of the first operand with the second operand by determining, for each result word index in a result word index range, a result data word for the result word index by accumulating products of sums of words of the first operand and the second operand and subtracting excess terms.
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公开(公告)号：US12019180B2
公开(公告)日：2024-06-25
申请号：US17305728
申请日：2021-07-14
发明人： Josef Kulmer , Ernst Seler , Hao Li , Gunther Kraut , Oleksiy Klymenko , Patrick Hoelzl
IPC分类号： G01S7/40 , G01S7/03 , G01S13/931
CPC分类号： G01S7/4017 , G01S7/032 , G01S13/931
摘要： According to a first example implementation, the method comprises providing a local oscillator signal in a first radar chip based on a local oscillator signal generated in a further radar chip; supplying the local oscillator signal to a transmission channel of the first radar chip which, based on the local oscillator signal, generates an HF output signal; changing the temperature and/or supply voltage of the first radar chip; measuring phase values based on the local oscillator signal supplied to the transmission channel and of the corresponding HF output signal for different temperature values and/or for different supply voltage values of the first radar chip; and ascertaining calibration data based on the measured phase values for a phase calibration to compensate for changes in the phase of the HF output signal resulting from a change in the temperature and/or in the supply voltage.
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公开(公告)号：US20240203950A1
公开(公告)日：2024-06-20
申请号：US18521372
申请日：2023-11-28
发明人： Christian MÜLLER , Jan BAURICHTER
IPC分类号： H01L25/07 , H01L23/00 , H01L23/498
CPC分类号： H01L25/072 , H01L23/49811 , H01L23/49822 , H01L23/49844 , H01L24/48 , H01L24/73 , H01L24/32 , H01L2224/32225 , H01L2224/48225 , H01L2224/73265 , H01L2924/1203 , H01L2924/13055 , H01L2924/13091
摘要： A power semiconductor module arrangement includes a substrate including a dielectric insulation layer and a first metallization layer arranged on a first side of the dielectric insulation layer, wherein the first metallization layer includes a plurality of different sections that are separate and distinct from each other, and a plurality of semiconductor bodies arranged on the first metallization layer, and including a first sub-group of semiconductor bodies and a second sub-group of semiconductor bodies, wherein the semiconductor bodies of the first sub-group differ from the semiconductor bodies of the second sub-group, wherein each of the plurality of semiconductor bodies includes a control electrode and a controllable load path between a first load electrode and a second load electrode, the first sub-group is symmetrical to the second sub-group.
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