Time-of-flight image sensor resolution enhancement and increased data robustness using a binning module

    公开(公告)号:US11570424B2

    公开(公告)日:2023-01-31

    申请号:US16449665

    申请日:2019-06-24

    发明人: Krum Beshinski

    摘要: A time-of-flight (ToF) image sensor system includes a pixel array, where each pixel of the pixel array is configured to receive a reflected modulated light signal and to demodulate the reflected modulated light signal to generate an electrical signal; a plurality of analog-to-digital converters (ADCs), where each ADC is coupled to at least one assigned pixel of the pixel array and is configured to convert a corresponding electrical signal generated by the at least one assigned pixel into an actual pixel value; and a binning circuit coupled to the plurality of ADCs and configured to generate at least one interpolated pixel, where the binning circuit is configured to generate each of the at least one interpolated pixel based on actual pixel values corresponding to a different pair of adjacent pixels of the pixel array, each of the at least one interpolated pixel having a virtual pixel value.

    Time-to-digital converter calibration

    公开(公告)号:US11569831B1

    公开(公告)日:2023-01-31

    申请号:US17656176

    申请日:2022-03-23

    摘要: A digital phase-locked loop (DPLL) may include a time-to-digital converter (TDC) to provide a phase error signal, a frequency-divider to perform frequency division on an output signal to generate a frequency-divided output signal, a delta-sigma-modulator (DSM) to provide a test signal that represents a quantization error of the DSM, and a digital-to-time converter (DTC) to at least partially remove the quantization error from the frequency-divided output signal based on the test signal to generate the feedback signal. The DPLL may include a circuit to cause the DTC to provide a percentage of the quantization error such that the percentage of the quantization error is in the phase error signal, and a TDC calibration component to calibrate the TDC by applying a gain adjustment factor to the TDC. The gain adjustment factor may be based on the test signal and the phase error signal including the percentage of the quantization error.

    Error detection for power converter

    公开(公告)号:US11569728B1

    公开(公告)日:2023-01-31

    申请号:US17456848

    申请日:2021-11-29

    摘要: A circuit for controlling a switch of a power converter includes a first clock signal generator configured to generate a first clock signal and a switching signal generator configured to generate a switching signal to control the switch of the power converter based on the first clock signal. The circuit further includes error detection circuitry configured to output an error indication and a second clock signal generator configured to generate, in response to the error indication, a second clock signal that comprises an edge of a clock cycle of the second clock signal that corresponds to when the switching signal deactivates the switch of the power converter plus a time delay. The switching signal generator is configured to generate the switching signal to control the switch of the power converter further based on the second clock signal in response to the error indication being output by the error detection circuitry.

    Apparatuses and method for light detection and ranging

    公开(公告)号:US11567175B2

    公开(公告)日:2023-01-31

    申请号:US16146200

    申请日:2018-09-28

    IPC分类号: G01S7/481 G01S7/484 G01S17/42

    摘要: An apparatus for light detection and ranging is provided. The apparatus includes a reflective surface configured to oscillate about a rotation axis, and a plurality of light sources each configured to controllably emit a respective light beam via an optical system onto the reflective surface. Further, the apparatus includes a controller configured to control emission times of the plurality of light sources so that the reflective surface emits a plurality of light beams to an environment according to a first sequence of beam directions for a first measurement, and according to a second sequence of beam directions for a subsequent second measurement.

    Power Module with Press-Fit Contacts

    公开(公告)号:US20230026022A1

    公开(公告)日:2023-01-26

    申请号:US17385731

    申请日:2021-07-26

    摘要: A method of forming a semiconductor device includes providing a substrate that comprises a metal region, forming an encapsulant body of electrically insulating material on an upper surface of the metal region, forming an opening in the encapsulant body, and inserting a press-fit connector into the opening, wherein after inserting the press-fit connector into the opening, the press-fit connector is securely retained to the substrate and an interfacing end of the press-fit connector is electrically accessible.

    Phase change switch with multi face heater configuration

    公开(公告)号:US11563174B2

    公开(公告)日:2023-01-24

    申请号:US16844450

    申请日:2020-04-09

    IPC分类号: H01L45/00

    摘要: A switching device includes first and second RF terminals disposed over a substrate, one or more strips of phase change material connected between the first and second RF terminals, a region of thermally insulating material that separates the one or more strips of phase change material from the substrate, and a heater structure comprising one or more heating elements that are configured to control a conductive connection between the first and second RF terminals by applying heat to the one or more strips of phase change material. Each of the one or more strips of phase change material includes a first outer face and a second outer face opposite from the first outer face. For each of the one or more strips of phase change material, at least portions of both of the first and second outer faces are disposed against one of the heating elements.

    Multiplexer for memory
    57.
    发明授权

    公开(公告)号:US11562789B2

    公开(公告)日:2023-01-24

    申请号:US17117713

    申请日:2020-12-10

    摘要: In an example, a multiplexer is provided. The multiplexer may include one or more first strings controlling access to source-lines of the memory, wherein a first string of the one or more first strings includes a first set of two high voltage transistors and a first plurality of low voltage transistors. The multiplexer may include one or more second strings controlling access to bit-lines of the memory, wherein a second string of the one or more second strings includes a second set of two high voltage transistors and a second plurality of low voltage transistors. A method for operating such multiplexer is provided.

    Signal compenstation system configured to measure and counteract asymmetry in hall sensors

    公开(公告)号:US11550004B2

    公开(公告)日:2023-01-10

    申请号:US16394304

    申请日:2019-04-25

    发明人: Udo Ausserlechner

    摘要: A sensor cross-talk compensation system includes a semiconductor substrate having a first main surface and a second main surface opposite to the first main surface; a vertical Hall sensor element disposed in the semiconductor substrate, the vertical Hall sensor element is configured to generate a sensor signal in response to a magnetic field impinging thereon; and an asymmetry detector configured to detect an asymmetric characteristic of the vertical Hall sensor element. The asymmetry detector includes a detector main region that vertically extends into the semiconductor substrate from the first main surface towards the second main surface and is of a conductivity type having a first doping concentration; and at least three detector contacts disposed in the detector main region at the first main surface, the at least three detector contacts are ohmic contacts of the conductivity type having a second doping concentration that is higher than the first doping concentration.

    Safety mechanism monitoring of autocalibrated compensation parameters

    公开(公告)号:US11550001B2

    公开(公告)日:2023-01-10

    申请号:US16788704

    申请日:2020-02-12

    IPC分类号: G01R33/00 G01B7/30 G06F11/00

    摘要: An autocalibration method includes generating at least one sensor signal in response to measuring a physical quantity; compensating the at least one sensor signal based on at least one compensation parameter to generate at least one compensated sensor signal; generating the at least one compensation parameter based on the at least one sensor signal or the at least one compensated sensor signal; comparing each of the at least one compensation parameter to a respective tolerance range; on a condition that each of the at least one compensation parameter is within its respective tolerance range, transmitting the at least one compensation parameter as at least one validated compensation parameter to be used for compensating the at least one sensor signal; and on a condition that at least one of the at least one compensation parameter is not within its respective tolerance range, generating a fault detection signal.