公开(公告)号：US20140266140A1

公开(公告)日：2014-09-18

申请号：US14205045

申请日：2014-03-11

Applicant: Analog Devices Technology

Inventor： Santiago Iriarte ,  Ramon Tortosa Navas ,  Enrique Company Bosch

IPC: G05F3/24

CPC classification number: G05F3/242 ,  G05F1/46 ,  G05F1/461 ,  G05F1/462 ,  G05F1/56 ,  G05F1/567

Abstract: A voltage generator is provided which is reliable, self starting and only requires a few components. The voltage generator comprises a first stage that provides a current to a second stage. The first stage has a temperature coefficient of one sign, such as positive, and the second stage has an opposing temperature coefficient, e.g. negative. The responses are summed such that the overall temperature coefficient is reduced.

Abstract translation: 提供电压发生器，可靠，自启动，只需要几个部件。 电压发生器包括向第二级提供电流的第一级。 第一阶段具有一个符号的温度系数，例如正的，第二阶段具有相反的温度系数，例如。 负。 将响应相加，使得总体温度系数降低。

公开(公告)号：US20140253061A1

公开(公告)日：2014-09-11

申请号：US13789210

申请日：2013-03-07

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Shanshan Yang ,  Guoming Wu ,  Bin Shao

IPC: G05F1/46

CPC classification number: G05F1/46 ,  H02M1/36 ,  H02M3/158 ,  H02M2001/0032 ,  Y02B70/16

Abstract: A method and system to inhibit the switching of a current mode switching converter having high and low side switching elements coupled to an output inductor, the other end of which is coupled to an output node, and operated with respective modulated switching signals to regulate an output voltage Vout produced at the node. A current IC that varies with the difference between a reference voltage and a voltage proportional to Vout is compared with and a current IDETECT—PEAK which varies with the current conducted by the high side switching element; the result of the comparison of IC and IDETECT—PEAK is used to control the regulation of Vout during normal operation. Current IC is also compared with a current IDETECT—VALLEY which varies with the current conducted by the low side switching element. When IDETECT—VALLEY>IC, a ‘skip mode’ is triggered during which the switching signals are inhibited.

Abstract translation: 一种抑制具有耦合到输出电感器的高低侧开关元件的电流模式切换转换器的方法和系统，该输出电感器的另一端耦合到输出节点，并且用相应的调制开关信号进行操作，以调节输出 在节点处产生的电压Vout。 与参考电压和与Vout成比例的电压之间的差异变化的电流IC与当前由高侧开关元件传导的电流变化的IDETECT-PEAK进行比较; IC和IDETECT-PEAK的比较结果用于控制正常工作期间Vout的调节。 电流IC还与当前的IDETECT-VALLEY进行比较，其随着低侧开关元件所传导的电流而变化。 当IDETECT-VALLEY> IC时，触发切换信号的“跳过模式”。

公开(公告)号：US08760201B1

公开(公告)日：2014-06-24

申请号：US13793438

申请日：2013-03-11

Applicant: Analog Devices Technology

Inventor： Ting Gao ,  Jiefeng Yan

IPC: H03L7/06

CPC classification number: H03L7/0895

Abstract: Systems and methods for capacitance multiplication using one charge pump for a phase lock loop employ a digital controlled loop filter that operates in a time division mode. Embodiments of the loop filter block the current from the charge pump according to the digital control, such that the charge pump cannot charge or discharge the integral capacitor when the digital control is enabled. Because at least a portion of the current is blocked, it takes more time for the charge pump to charge or discharge the capacitor to a certain level. The capacitor then appears to be larger than its actual value with respect to operation of the phase lock loop.

Abstract translation: 使用一个用于锁相环的电荷泵进行电容倍增的系统和方法采用以时分模式工作的数字控制环路滤波器。 环路滤波器的实施例根据数字控制阻挡来自电荷泵的电流，使得当数字控制被使能时，电荷泵不能对积分电容器充电或放电。 因为电流的至少一部分被阻塞，所以电荷泵将电容器充电或放电到一定水平需要更多的时间。 相对于锁相环的操作，电容器似乎大于其实际值。

公开(公告)号：US20140074901A1

公开(公告)日：2014-03-13

申请号：US14055177

申请日：2013-10-16

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Andreas D. Olofsson ,  Baruch Yanovitch

IPC: G06F17/10

CPC classification number: G06F17/10 ,  G06F7/5324 ,  G06F9/3001 ,  G06F9/30036 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/383 ,  G06F9/3885

Abstract: Multiplication engines and multiplication methods are provided for a digital processor. A multiplication engine includes multipliers, each receiving a first operand and a second operand; a local operand register having locations to hold the first operands for respective multipliers; a first operand bus coupled to the local operand register to supply the first operands from a compute register file to the local operand register; a second operand bus coupled to the plurality of multipliers to supply one or more of to the second operands from the compute register file to respective multipliers; and a control unit responsive to a digital processor instruction to supply the first operands from the local operand register to respective multipliers, to supply the second operands from the compute register file to respective multipliers on the second operand bus and to multiply the first operands by the respective second operands in the respective multipliers, wherein one or more of the first operands in the local operand register are reused by the multipliers in two or more multiplication operations.

Abstract translation: 为数字处理器提供乘法引擎和乘法方法。 乘法引擎包括乘法器，每个乘法器接收第一操作数和第二操作数; 本地操作数寄存器，其具有用于保持各乘法器的第一操作数的位置; 耦合到本地操作数寄存器的第一操作数总线，用于将第一操作数从计算寄存器文件提供给本地操作数寄存器; 耦合到所述多个乘法器的第二操作数总线，以将所述第二操作数中的一个或多个从计算寄存器文件提供给各个乘法器; 以及控制单元，其响应于数字处理器指令将第一操作数从本地操作数寄存器提供给各个乘法器，以将第二操作数从计算寄存器文件提供给第二操作数总线上的相应乘法器，并将第一操作数乘以 各个乘法器中的相应的第二操作数，其中本地操作数寄存器中的第一操作数中的一个或多个在两个或多个乘法运算中由乘法器重新使用。

公开(公告)号：US09755602B2

公开(公告)日：2017-09-05

申请号：US14258634

申请日：2014-04-22

Applicant: Analog Devices Technology ,  Analog Devices, Inc.

Inventor： Eberhard Brunner ,  Jeff Venuti

IPC: H04B1/04 ,  H03G3/30 ,  H03F3/19 ,  H03F3/45 ,  H03G1/00 ,  H03C1/62

CPC classification number: H03G3/3042 ,  H03F3/19 ,  H03F3/4508 ,  H03F2200/336 ,  H03F2200/451 ,  H03F2203/45116 ,  H03F2203/45154 ,  H03F2203/45306 ,  H03G1/0023

Abstract: A system has a baseband gain stage to receive incoming in-phase and quadrature voltage signals and output in-phase and quadrature current signals, a mixer core arranged to receive the in-phase and quadrature current signals and output radio frequency signals, and a variable gain amplifier to receive the radio frequency signals and produce a broadband radio signal.

公开(公告)号：US09460354B2

公开(公告)日：2016-10-04

申请号：US13888993

申请日：2013-05-07

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Joseph Fernandez ,  Sreenath Kottekkode

IPC: G06K9/00 ,  G06K9/46 ,  G06K9/66 ,  G06K9/62 ,  H04N7/18

CPC classification number: G06K9/00805 ,  G06K9/00791 ,  G06K9/4642 ,  G06K9/6269

Abstract: Objects are detected in real-time at full VGA 30 frame per second resolution. A preprocessor performs run-length encoding (RLE) and generates a summed area table (SAT) of an image. The RLE and SAT are used to identify candidate objects and to iteratively refine their boundaries. A histogram of gradients (HoG) and support vector machine (SVM) then reliably classify the object. The method may be part of an advanced driver assistance system (ADAS).

Abstract translation: 实时检测物体的全VGA每秒30帧分辨率。 预处理器执行游程长度编码（RLE）并生成图像的求和区域表（SAT）。 RLE和SAT用于识别候选对象并迭代地改进边界。 梯度（HoG）和支持向量机（SVM）的直方图然后可靠地对对象进行分类。 该方法可以是高级驾驶员辅助系统（ADAS）的一部分。

公开(公告)号：US09350308B2

公开(公告)日：2016-05-24

申请号：US14296247

申请日：2014-06-04

Applicant: Analog Devices Technology

Inventor： Eberhard Brunner

IPC: H03F3/45 ,  H03G1/00 ,  H03F3/04

CPC classification number: H03G1/0017 ,  H03F3/04 ,  H03F3/45 ,  H03F3/45085 ,  H03F2203/45274 ,  H03F2203/45392 ,  H03F2203/45601 ,  H03F2203/45612 ,  H03G1/0023

Abstract: A transconductance gain stage including a pair of gain transistors, each gain transistor having a base and an emitter, the emitter of each gain transistor electrically coupled to a degenerating resistor, and the emitter of each gain transistor connected to a gain resistor.

Abstract translation: 跨导增益级包括一对增益晶体管，每个增益晶体管具有基极和发射极，每个增益晶体管的发射极电耦合到退化电阻器，并且每个增益晶体管的发射极连接到增益电阻器。

公开(公告)号：US09292763B2

公开(公告)日：2016-03-22

申请号：US13951193

申请日：2013-07-25

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Bijesh Poyil ,  Ramandeep Singh Kukreja ,  Anil M. Sripadarao

IPC: G06K9/46 ,  G06K9/48 ,  G06T7/00

CPC classification number: G06K9/48 ,  G06K9/4638 ,  G06T7/11 ,  G06T7/12 ,  G06T7/13 ,  G06T7/136 ,  G06T7/181 ,  G06T7/194 ,  G06T2200/28

Abstract: A method includes determining a position and length of a non-zero run in a row of a pixel map. The method also includes determining a number of neighbors for the non-zero run in a preceding row, based at least in part on the position and the length. In addition, the method includes updating a correspondence map of the non-zero run and a correspondence map of a first neighbor of the non-zero run, based at least in part on a correspondence map of a second neighbor of the non-zero run, in response to a determination that the non-zero run has at least two neighbors in the preceding row.

Abstract translation: 一种方法包括确定像素图的一行中的非零运行的位置和长度。 该方法还包括至少部分地基于位置和长度来确定前一行中的非零运行的数量的邻居。 另外，该方法至少部分地基于非零运行的第二邻居的对应关系图来更新非零运行的对应关系图和非零运行的第一邻居的对应关系图 响应于确定非零运行在前一行中具有至少两个邻居。

公开(公告)号：US20160034399A1

公开(公告)日：2016-02-04

申请号：US14450145

申请日：2014-08-01

Applicant: Analog Devices Technology

Inventor： Abhijit Giri ,  Saurbh Srivastava ,  Michael S. Allen

IPC: G06F12/08

CPC classification number: G06F12/0848 ,  G06F2212/1024

Abstract: Digital signal processors often operate on two operands per instruction, and it is desirable to retrieve both operands in one cycle. Some data caches connect to the processor over two busses and internally uses two or more memory banks to store cache lines. The allocation of cache lines to specific banks is based on the address that the cache line is associated. When two memory accesses map to the same memory bank, fetching the operands incurs extra latency because the accesses are serialized. An improved bank organization for providing conflict-free dual-data cache access—a bus-based data cache system having two data buses and two memory banks—is disclosed. Each memory bank works as a default memory bank for the corresponding data bus. As long as the two values of data being accessed belong to two separate data sets assigned to the two respective data buses, memory bank conflicts are avoided.

Abstract translation: 数字信号处理器通常在每个指令的两个操作数上操作，并且期望在一个周期内检索两个操作数。 一些数据高速缓存通过两个总线连接到处理器，并且内部使用两个或多个存储体来存储高速缓存行。 将高速缓存行分配给特定存储区基于高速缓存行关联的地址。 当两个内存访问映射到同一个存储区时，获取操作数会导致额外的延迟，因为访问是序列化的。 公开了一种用于提供无冲突双数据高速缓存访​​问的改进的银行组织 - 具有两个数据总线和两个存储体的基于总线的数据高速缓存系统。 每个存储体都作为相应数据总线的默认存储体。 只要访问的数据的两个值属于分配给两个相应的数据总线的两个单独的数据集，就避免了存储体冲突。

公开(公告)号：US09148168B2

公开(公告)日：2015-09-29

申请号：US14065732

申请日：2013-10-29

Applicant: ANALOG DEVICES TECHNOLOGY

Inventor： Zhao Li ,  David Alldred

IPC: H03M1/10 ,  H03M3/00 ,  H03M1/12 ,  H03M1/00

CPC classification number: H03M3/368 ,  H03M1/00 ,  H03M1/12 ,  H03M3/30 ,  H03M3/38 ,  H03M3/424 ,  H03M3/454

Abstract: An analog-to-digital converter (ADC) can include a continuous-time delta sigma modulator and calibration logic. The calibration logic can calibrate direct feedback and flash clock delay coefficients of the continuous-time delta-sigma modulator without interrupting the normal operations of the ADC (e.g., in situ). Thus, the calibration logic can rectify performance and stability degradation by calibrating suboptimal coefficients.

Abstract translation: 模数转换器（ADC）可以包括连续时间ΔΣ调制器和校准逻辑。 校准逻辑可以校准连续时间Δ-Σ调制器的直接反馈和闪速时钟延迟系数，而不中断ADC的正常操作（例如，原位）。 因此，校准逻辑可以通过校准次优系数来纠正性能和稳定性降级。