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公开(公告)号：US20210243450A1
公开(公告)日：2021-08-05
申请号：US17236910
申请日：2021-04-21
申请人： ATI Technologies ULC
发明人： Mehdi Saeedi , Boris Ivanovic
IPC分类号： H04N19/14 , H04N19/513 , H04N19/176
摘要： Systems, apparatuses, and methods for implementing spatial block-level pixel activity extraction optimization leveraging motion vectors are disclosed. Control logic coupled to an encoder generates block-level pixel activity metrics for a new frame based on the previously calculated block-level pixel activity data from a reference frame. A cost is calculated for each block of a new frame with respect to a corresponding block of the reference frame. If the cost is less than a first threshold, then the control logic generates an estimate of a pixel activity metric for the block which is equal to a previously calculated pixel activity metric for a corresponding block of the reference frame. If the cost is greater than the first threshold but less than a second threshold, an estimate of the pixel activity metric is generated by extrapolating from the previously calculated pixel activity metric.
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公开(公告)号：US11079945B2
公开(公告)日：2021-08-03
申请号：US16137413
申请日：2018-09-20
申请人： ATI TECHNOLOGIES ULC
发明人： Omer Irshad , Joohyun Lee
IPC分类号： G06F3/00 , G06F3/06 , G06T1/60 , G06F3/0484 , G06F9/4401 , G06F13/16 , G06T1/20 , G06F3/0482
摘要： A processing system includes a memory controller coupleable to a RAM, and a ROM configured to store boot information that includes default values for a set of one or more memory timing parameters. At least one processor is configured to, during initialization, configure the memory controller to utilize the default values for the set of one or more memory timing parameters. The at least one processor further is configured to, during operation of the processing system following initialization, receive user input representing one or more updated values for one or more corresponding memory timing parameters of the set, and to dynamically reconfigure the memory controller to utilize one or more updated values for the set of one or more memory timing parameters for the signaling. The processing system further is configured to conduct one or more memory access operations for the RAM using the reconfigured memory controller.
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公开(公告)号：US20210233205A1
公开(公告)日：2021-07-29
申请号：US17230129
申请日：2021-04-14
申请人： ATI Technologies ULC
摘要： A graphics processing architecture in one example performs vertex manipulation operations and pixel manipulation operations by transmitting vertex data to a general purpose register block, and performing vertex operations on the vertex data by a processor unless the general purpose register block does not have enough available space therein to store incoming vertex data; and continues pixel calculation operations that are to be or are currently being performed by the processor based on instructions maintained in an instruction store until enough registers within the general purpose register block become available.
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公开(公告)号：US20210209831A1
公开(公告)日：2021-07-08
申请号：US17208730
申请日：2021-03-22
发明人： Michael Mantor , Laurent Lefebvre , Mikko Alho , Mika Tuomi , Kiia Kallio
摘要： A method, system, and non-transitory computer readable storage medium for rasterizing primitives are disclosed. The method, system, and non-transitory computer readable storage medium includes: generating a primitive batch from a sequence of one or more primitives, wherein the primitive batch includes primitives sorted into one or more row groups based on which row of a plurality of rows each primitive intersects; and processing each row group, the processing for each row group including: identifying one or more primitive column intercepts for each of the one or more primitives in the row group, wherein each combination of primitive column intercept and row identifies a bin; and rasterizing the one or more primitives that intersect the bin.
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公开(公告)号：US11055242B2
公开(公告)日：2021-07-06
申请号：US15192723
申请日：2016-06-24
申请人： ATI Technologies ULC
发明人： Gordon Caruk , Jaroslaw Marczewski
摘要： Methods and devices for handling short Peripheral Component Interconnect Express (PCIe) Transaction Layer Packets (TLPs) are described. A receiver can receive at least a portion of a first packet and can process the first packet to determine if the first packet is a short packet. The receiver can receive at least a portion of a second packet and if the first packet is a short packet, the receiver can transmit a negative acknowledgement (NAK) in response to the second packet and can receive a retransmission of the second packet.
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公开(公告)号：US11054883B2
公开(公告)日：2021-07-06
申请号：US16011476
申请日：2018-06-18
IPC分类号： G06F1/324
摘要： A power management algorithm framework proposes: 1) a Quality-of-Service (QoS) metric for throughput-based workloads; 2) heuristics to differentiate between throughput and latency sensitive workloads; and 3) an algorithm that combines the heuristic and QoS metric to determine target frequency for minimizing idle time and improving power efficiency without any performance degradation. A management algorithm framework enables optimizing power efficiency in server-class throughput-based workloads while still providing desired performance for latency sensitive workloads. The power savings are achieved by identifying workloads in which one or more cores can be run at a lower frequency (and consequently lower power) without a significant negative performance impact.
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公开(公告)号：US20210185313A1
公开(公告)日：2021-06-17
申请号：US16715187
申请日：2019-12-16
申请人： ATI Technologies ULC
发明人： Boris Ivanovic , Mehdi Saeedi
IPC分类号： H04N19/115 , G06N5/04 , H04N19/176 , H04N19/159
摘要： Systems, apparatuses, and methods for using residual metrics for encoder rate control are disclosed. An encoder includes a mode decision unit for determining a mode to be used for generating a predictive block for each block of a video frame. For each block, control logic calculates a residual of the block by comparing an original version of the block to the predictive block. The control logic generates a residual metric based on the residual and based on the mode. The encoder's rate controller selects a quantization strength setting for the block based on the residual metric. Then, the encoder generates an encoded block that represents the input block by encoding the block with the selected quantization strength setting. Next, the encoder conveys the encoded block to a decoder to be displayed. The encoder repeats this process for each block of the frame.
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公开(公告)号：US11037357B2
公开(公告)日：2021-06-15
申请号：US16706308
申请日：2019-12-06
发明人： Ruijin Wu , Skyler Jonathon Saleh , Christopher J. Brennan , Kei Ming Kwong , Anthony Hung-Cheong Chan
摘要： A technique for compressing an original image is disclosed. According to the technique, an original image is obtained and a delta-encoded image is generated based on the original image. Next, a segregated image is generated based on the delta-encoded image and then the segregated image is compressed to produce a compressed image. The segregated image is generated because the segregated image may be compressed more efficiently than the original image and the delta image.
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公开(公告)号：US11036658B2
公开(公告)日：2021-06-15
申请号：US16249649
申请日：2019-01-16
摘要： Systems, methods, and port controller designs employ a light-weight memory protocol. A light-weight memory protocol controller is selectively coupled to a Cache Coherent Interconnect for Accelerators (CCIX) port. Over an on-chip interconnect fabric, the light-weight protocol controller receives memory access requests from a processor and, in response, transmits associated memory access requests to an external memory through the CCIX port using only a proper subset of CCIX protocol memory transactions types including non-cacheable transactions and non-snooping transactions. The light-weight memory protocol controller is selectively uncoupled from the CCIX port and a remote coherent slave controller is coupled in its place. The remote coherent slave controller receives memory access requests and, in response, transmits associated memory access requests to a memory module through the CCIX port using cacheable CCIX protocol memory transaction types.
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公开(公告)号：US20210150797A1
公开(公告)日：2021-05-20
申请号：US17008388
申请日：2020-08-31
摘要： Systems, apparatuses, and methods for implementing light volume rendering techniques are disclosed. A processor is coupled to a memory. A processor renders the geometry of a scene into a geometry buffer. For a given light source in the scene, the processor initiates two shader pipeline passes to determine which pixels in the geometry buffer to light. On the first pass, the processor renders a front-side of a light volume corresponding to the light source. Any pixels of the geometry buffer which are in front of the front-side of the light volume are marked as pixels to be discarded. Then, during the second pass, only those pixels which were not marked to be discarded are sent to the pixel shader. This approach helps to reduce the overhead involved in applying a lighting effect to the scene by reducing the amount of work performed by the pixel shader.
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