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公开(公告)号：US11815534B2
公开(公告)日：2023-11-14
申请号：US17678345
申请日：2022-02-23
Inventor： Tahir Rashid , Mehul Mistry
CPC classification number: G01R19/0023 , H03G3/3042
Abstract: This invention relates to current sensing, in particular for a signal processing circuit (500) for outputting an output signal (Sout) based on an input signal (Sin). An output stage (101) includes an output transistor (102) driven, in use, by a drive signal. A current monitor (501) is configured to monitor, in use, a first current through the output transistor, wherein the current monitor comprises a current sensor (105) having a sense transistor (106) configured to be driven based on the drive signal so as to generate a sense current related to the first current. A compensation controller (301) receives an indication of signal level of the input signal and controllably varies operation of the current monitor (501) so as to at least partially compensate for signal-dependent variation in a relationship between the first current and the first sense current.
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公开(公告)号：US11814284B2
公开(公告)日：2023-11-14
申请号：US16825593
申请日：2020-03-20
Inventor： Roberto Brioschi , Rkia Achehboune
CPC classification number: B81C1/0023 , B81B3/0021 , B81C1/00253 , H01L24/19 , H04R19/005 , B81B2201/0257 , B81B2201/0264 , B81B2203/0127 , H01L2924/1461 , H04R2201/003
Abstract: The application relates to structures, e.g. substrates for supporting semiconductor die. The substrate defines a frame which lateral surrounds one or more die and is provided in contact with at least one side surface of the die, wherein the frame defines upper and lower surfaces of the substrate.
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公开(公告)号：US11810544B2
公开(公告)日：2023-11-07
申请号：US17705974
申请日：2022-03-28
Inventor： Brenton Steele
IPC: G10K11/178 , H04R3/00
CPC classification number: G10K11/17881 , H04R3/002 , H04R3/007 , G10K2210/1081 , G10K2210/3028 , G10K2210/3226
Abstract: Embodiments generally relate to a signal processing device for on ear detection for a headset. The device comprises a first microphone input for receiving a microphone signal from a first microphone, the first microphone being configured to be positioned inside an ear of a user when the user is wearing the headset; a second microphone input for receiving a microphone signal from a second microphone, the second microphone being configured to be positioned outside the ear of the user when the user is wearing the headset; and a processor. The processor is configured to receive microphone signals from each of the first microphone input and the second microphone input; pass the microphone signals through a first filter to remove low frequency components, producing first filtered microphone signals; combine the first filtered microphone signals to determine a first on ear status metric; pass the microphone signals through a second filter to remove high frequency components, producing second filtered microphone signals; combine the second filtered microphone signals to determine a second on ear status metric; and combine the first on ear status metric with the second on ear status metric to determine the on ear status of the headset.
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公开(公告)号：US20230353937A1
公开(公告)日：2023-11-02
申请号：US17983000
申请日：2022-11-08
Inventor： Andrew J. HOWLETT , Michael CHANDLER-PAGE , Lea S. GEORGIEVA
CPC classification number: H04R3/04 , H03G3/3005 , H04R2430/01
Abstract: Signal processing circuitry configured to receive an input signal and to output a processed output signal, wherein the signal processing circuitry is configured to: receive an indication of a temporal location of a transient in the input signal; and provide, in the processed output signal, a masking signal bridging the temporal location of the transient to mask the transient.
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公开(公告)号：US11804813B2
公开(公告)日：2023-10-31
申请号：US17386287
申请日：2021-07-27
Inventor： John Paul Lesso , Toru Ido
CPC classification number: H03G3/3089 , H03F1/26 , H03F1/32 , H03F1/34 , H03F3/187 , H03F3/217 , H03F3/2175 , H03G7/002 , H03G7/007 , H03F3/2171 , H03F3/2173 , H03F2200/102 , H03F2200/339 , H03F2200/432
Abstract: This application relates to Class D amplifier circuits. A modulator controls a Class D output stage based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block, which may comprise an ADC, generates an error signal (ε) from the output signal and the input signal. In various embodiments the extent to which the error signal (ε) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input of a signal selector block. The input signal may be received at a second input of the signal selector block. The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block.
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Patent Agency Ranking
56.发明公开公开(公告)号：US20230344394A1
公开(公告)日：2023-10-26
申请号：US18303750
申请日：2023-04-20
Inventor： John L. MELANSON , Abhishek MUKHERJEE , Lingli ZHANG , Zhaohui HE
CPC classification number: H03F3/2175 , H03F1/3264 , H03F1/0255 , H03F2200/351 , H03F2200/03
Abstract: A system may include an analog loop filter comprising a plurality of analog integrators, the analog loop filter configured to receive an analog signal input and a feedback output signal, at least one sampler for sampling outputs of the analog integrators, a second loop filter coupled between an output of an analog pulse-width modulation driver and a digital pulse-width modulation controller, wherein the second loop filter comprises at least one integrator and is configured to receive sampled outputs of the analog integrators from the at least one sampler and receive a feedback pulse-width modulation signal from the analog pulse-width modulation driver, and a correction subsystem configured to apply a non-linear function to a signal path of the second loop filter in order to compensate for non-linearity introduced as a result of sampling outputs of the analog integrators.
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公开(公告)号：US20230341348A1
公开(公告)日：2023-10-26
申请号：US17725995
申请日：2022-04-21
Inventor： John P. LESSO
IPC: G01N27/327 , H03M1/12 , A61B5/1468 , A61B5/1486 , A61B5/145 , A61B5/00
CPC classification number: G01N27/3273 , H03M1/125 , A61B5/1468 , A61B5/1486 , A61B5/14532 , A61B5/14542 , A61B5/14546 , A61B5/0002 , A61B2560/0209
Abstract: Circuitry for processing an analyte signal obtained from an electrochemical cell, the circuitry comprising: a first analog-to-digital converter (ADC) configured to generate a first digital output based on the analyte signal; a second ADC configured to generate a second digital output based on the analyte signal; and control circuitry configured to control generation of the second digital output by the second ADC based on the first digital output from the first ADC.
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公开(公告)号：US20230336132A1
公开(公告)日：2023-10-19
申请号：US17720869
申请日：2022-04-14
Inventor： John L. MELANSON
IPC: H03F3/217
CPC classification number: H03F3/217 , H03F2200/03 , H03F2200/375
Abstract: A switched mode amplifier system may include a switched mode amplifier having an amplifier input coupled to an output of an analog integrator and an amplifier output and include a calibration system. The calibration system may be configured to force the input of the analog integrator to a fixed known input value, force the amplifier output to a fixed known duty cycle, measure an analog signal generated at the output of the analog integrator in response to forcing the input of the analog integrator to the fixed value, determine an offset of the switched mode amplifier system based on the analog signal, and correct for the offset.
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59.发明公开公开(公告)号：US20230336013A1
公开(公告)日：2023-10-19
申请号：US18295530
申请日：2023-04-04
Inventor： Emmanuel A. MARCHAIS , Eric J. KING , John L. MELANSON
IPC: G01R31/367 , G01R31/389 , H02J7/00
CPC classification number: H02J7/0068 , G01R31/367 , G01R31/389
Abstract: A method of adapting a battery charging profile of a battery may include monitoring one or more parameters associated with the battery during normal operation of a device powered from the battery and while the battery is simultaneously charged by a charger and is discharged by a dynamic system load of the device, determining an impedance of the battery based on the one or more parameters, determining a condition of the battery based on the impedance and the one or more parameters, and adapting the battery charging profile based on the condition.
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公开(公告)号：US11792569B2
公开(公告)日：2023-10-17
申请号：US18101816
申请日：2023-01-26
Inventor： Anthony S. Doy , Eric J. King
IPC: H04R3/00 , H03K17/687 , H03F3/217
CPC classification number: H04R3/00 , H03K17/687 , H03F3/217
Abstract: The application describes a switched driver (401) for outputting a drive signal at an output node (402) to drive a load such as a transducer. The driver receives respective high-side and low-side voltages (VinH, VinL) defining an input voltage at first and second input nodes and has connections for first and second capacitors (403H, 403L). A network of switching paths is configured such that each of the first and second capacitors can be selectively charged to the input voltage, the first input node can be selectively coupled to a first node (N1) by a path that include or bypass the first capacitor, and the second input node can be selectively coupled to a second node (N2) by a path that includes or bypasses the second capacitor. The output node (402) can be switched between two switching voltages at the first or second nodes. The driver is selectively operable in different operating modes, where the switching voltages are different in each of said modes.
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