公开(公告)号：US10060963B2

公开(公告)日：2018-08-28

申请号：US15471199

申请日：2017-03-28

Applicant: Cascade Microtech, Inc.

Inventor： Timothy Allen McMullen ,  Jeffery Allan Shepler ,  Clint Vander Giessen

IPC: G01R31/00

CPC classification number: G01R31/003 ,  G01R31/2863 ,  G01R31/2874

Abstract: Probe systems, storage media, and methods for wafer-level testing over extended temperature ranges are disclosed herein. The methods are configured to test a plurality of devices under test (DUTs) present on a substrate. The probe systems are programmed to perform the methods. The storage media include computer-readable instructions that direct a probe system to perform the methods.

公开(公告)号：US09983232B2

公开(公告)日：2018-05-29

申请号：US14491606

申请日：2014-09-19

Applicant: Cascade Microtech, Inc.

Inventor： Frank-Michael Werner ,  Matthias Zieger ,  Sebastian Giessmann

IPC: G01R1/073 ,  G01R31/28 ,  G01R1/04

CPC classification number: G01R1/073 ,  G01R1/04 ,  G01R31/2891

Abstract: A prober for testing devices in a repeat structure on a substrate is provided with a probe holder plate, probe holders mounted on the plate, and a test probe associated with each holder. Each test probe is displaceable via a manipulator connected to a probe holder, and a substrate carrier fixedly supports the substrate. Testing of devices, which are situated in a repeat structure on a substrate, in sequence without a substrate movement and avoiding individual manipulation of the test probes in relation to the contact islands on the devices, is achieved in that the probe holders are fastened on a shared probe holder plate and the probe holder plate is moved in relation to the test substrate.

公开(公告)号：US20180088149A1

公开(公告)日：2018-03-29

申请号：US15708681

申请日：2017-09-19

Applicant: Cascade Microtech, Inc.

Inventor： Gavin Neil Fisher ,  Thomas Reiner Thaerigen ,  Peter McCann ,  Rodney Jones ,  Koby L. Duckworth

IPC: G01R1/067

CPC classification number: G01R1/06794 ,  G01R1/07364 ,  G01R31/2891 ,  G01R35/00

Abstract: Probe systems and methods are disclosed herein. The methods include directly measuring a distance between a first manipulated assembly and a second manipulated assembly, contacting first and second probes with first and second contact locations, providing a test signal to an electrical structure, and receiving a resultant signal from the electrical structure. The methods further include characterizing at least one of a probe system and the electrical structure based upon the distance. In one embodiment, the probe systems include a measurement device configured to directly measure a distance between a first manipulated assembly and a second manipulated assembly. In another embodiment, the probe systems include a probe head assembly including a platen, a manipulator operatively attached to the platen, a vector network analyzer (VNA) extender operatively attached to the manipulator, and a probe operatively attached to the VNA extender.

公开(公告)号：US20180031608A1

公开(公告)日：2018-02-01

申请号：US15725650

申请日：2017-10-05

Applicant: Cascade Microtech, Inc.

Inventor： Michael Teich ,  Karsten Stoll ,  Walter Matthias Clauss ,  Swen Schmiedchen

IPC: G01R1/18 ,  G01R1/44 ,  G01R1/067

CPC classification number: G01R1/18 ,  G01N27/42 ,  G01N31/02 ,  G01R1/06711 ,  G01R1/07378 ,  G01R1/07392 ,  G01R1/44

Abstract: Shielded probe systems are disclosed herein. The shielded probe systems are configured to test a device under test (DUT) and include an enclosure that defines an enclosure volume, a translation stage with a stage surface, a substrate-supporting assembly extending from the stage surface, an electrically conductive shielding structure, an isolation structure, and a thermal shielding structure. The substrate-supporting assembly includes an electrically conductive support surface, which is configured to support a substrate that includes the DUT. The electrically conductive shielding structure defines a shielded volume. The isolation structure electrically isolates the electrically conductive shielding structure from the enclosure and from the translation stage. The thermal shielding structure extends within the enclosure volume and at least partially between the enclosure and the substrate-supporting assembly.

公开(公告)号：US20170292974A1

公开(公告)日：2017-10-12

申请号：US15094716

申请日：2016-04-08

Applicant: Cascade Microtech, Inc.

Inventor： Michael Teich ,  Karsten Stoll ,  Walter Matthias Clauss ,  Swen Schmiedchen

IPC: G01R1/18 ,  G01R1/44 ,  G01R1/067

CPC classification number: G01R1/18 ,  G01N27/42 ,  G01N31/02 ,  G01R1/06711 ,  G01R1/07378 ,  G01R1/07392 ,  G01R1/44

Abstract: Shielded probe systems are disclosed herein. The shielded probe systems are configured to test a device under test (DUT) and include an enclosure that defines an enclosure volume, a translation stage with a stage surface, a substrate-supporting stack extending from the stage surface, an electrically conductive shielding structure, an isolation structure, and a thermal shielding structure. The substrate-supporting stack includes an electrically conductive support surface and a temperature-controlled chuck. The electrically conductive shielding structure defines a shielded volume. The isolation structure electrically isolates the electrically conductive shielding structure from the enclosure and from the translation stage. The thermal shielding structure extends within the enclosure volume and at least partially between the enclosure and the substrate-supporting stack.

公开(公告)号：US09470753B2

公开(公告)日：2016-10-18

申请号：US14071388

申请日：2013-11-04

Applicant: CASCADE MICROTECH, INC.

Inventor： Daniel M. Bock ,  Kenneth R. Smith

IPC: G01R31/28 ,  G01R31/317

CPC classification number: G01R31/31715 ,  G01R31/28

Abstract: Systems and methods for testing a device under test (DUT) that includes a low power output driver. The methods include providing an input signal to the DUT. The low power output driver is configured to generate a data signal responsive to receipt of the input signal by the DUT and provide the data signal to a signal analyzer via a data signal transmission line. The methods further include determining an expected data signal to be received from the low power output driver and charging at least a portion of the data signal transmission line with a co-drive output signal that is based, at least in part, on the expected data signal. The methods further include receiving a composite data signal with the signal analyzer. The systems include probe heads with a plurality of data signal transmission lines and a plurality of co-drive conductors.

Abstract translation: 用于测试包含低功率输出驱动器的被测设备（DUT）的系统和方法。 所述方法包括向DUT提供输入信号。 低功率输出驱动器被配置为响应于DUT接收到输入信号而生成数据信号，并且经由数据信号传输线将数据信号提供给信号分析器。 所述方法还包括确定要从低功率输出驱动器接收的期望数据信号，并且至少部分地基于预期数据对共驱动输出信号进行数据信号传输线的至少一部分的充电 信号。 所述方法还包括用信号分析器接收复合数据信号。 该系统包括具有多个数据信号传输线和多个共驱动导体的探头。

公开(公告)号：US09429638B2

公开(公告)日：2016-08-30

申请号：US13854725

申请日：2013-04-01

Applicant: CASCADE MICROTECH, INC.

Inventor： Kenneth R. Smith

IPC: H01R43/20 ,  G01R35/00 ,  G01R1/067 ,  B32B38/10 ,  G01R1/073

CPC classification number: G01R31/2891 ,  B32B38/10 ,  G01R1/06711 ,  G01R1/06772 ,  G01R1/0735 ,  G01R35/00 ,  Y10T29/49126

Abstract: The contacts of a probing apparatus are elastically supported on a replaceable coupon and electrically interconnected with conductors on a membrane or a space transformer.

Abstract translation: 探测装置的触点弹性地支撑在可更换的试样上并与膜或空间变压器上的导体电互连。

公开(公告)号：US09373533B2

公开(公告)日：2016-06-21

申请号：US14141812

申请日：2013-12-27

Applicant: Cascade Microtech, Inc.

Inventor： Frank Fehrmann ,  Botho Hirschfeld ,  Stojan Kanev

IPC: G01R31/20 ,  H01L21/677

CPC classification number: H01L21/67745 ,  H01L21/67775

Abstract: Systems and methods for providing wafer access in a wafer processing system are disclosed herein. The methods may include docking a first wafer cassette on the wafer processing system and removing a selected wafer from the first wafer cassette with the wafer processing system. The methods further may include performing a process operation on the selected wafer with the wafer processing system and undocking the first wafer cassette from the wafer processing system while performing the process operation. The methods also may include docking a second wafer cassette (which may be the same as or different from the first wafer cassette) on the wafer processing system, inventorying the second wafer cassette with the wafer processing system, and/or subsequently placing the selected wafer in the second wafer cassette. The systems may include wafer processing systems that include a controller that is programmed to perform at least a portion of the methods.

Abstract translation: 本文公开了在晶片处理系统中提供晶片访问的系统和方法。 所述方法可以包括将晶片处理系统上的第一晶片盒对接，并且利用晶片处理系统从第一晶片盒移除选定的晶片。 该方法还可以包括使用晶片处理系统在所选择的晶片上执行处理操作，并且在执行处理操作时从晶片处理系统脱离第一晶片盒。 所述方法还可以包括将第二晶片盒（其可以与第一晶片盒相同或不同）对准在晶片处理系统上，利用晶片处理系统盘存第二晶片盒，和/或随后将所选择的晶片 在第二晶片盒中。 系统可以包括晶片处理系统，其包括被编程为执行方法的至少一部分的控制器。

公开(公告)号：US20150114925A1

公开(公告)日：2015-04-30

申请号：US14592749

申请日：2015-01-08

Applicant: Cascade Microtech, Inc.

Inventor： Kenneth R. Smith ,  Mike Jolley ,  Eric Strid ,  Peter Hanaway ,  K. Reed Gleason ,  Koby L. Duckworth

IPC: H01L21/48

CPC classification number: G01R1/0735 ,  G01R1/06727 ,  G01R1/06733 ,  G01R1/07342 ,  H01L21/4825 ,  H01L21/4828 ,  H01L21/4842 ,  H01L21/4853 ,  H01L21/4857 ,  Y10T29/49155

Abstract: Resilient electrical interposers that may be utilized to form a plurality of electrical connections between a first device and a second device, as well as systems that may utilize the resilient electrical interposers and methods of use and/or fabrication thereof. The resilient electrical interposers may include a resilient dielectric body with a plurality of electrical conduits contained therein. The plurality of electrical conduits may be configured to provide a plurality of electrical connections between a first surface of the electrical interposer and/or the resilient dielectric body and a second, opposed, surface of the electrical interposer and/or the resilient dielectric body. The systems and methods disclosed herein may provide for improved vertical compliance, improved contact force control, and/or improved dimensional stability of the resilient electrical interposers.

Abstract translation: 可用于在第一装置和第二装置之间形成多个电连接的弹性电插入件，以及可利用弹性电插入件及其使用和/或制造方法的系统。 弹性电插入件可以包括弹性介电体，其中包含多个电导管。 多个电导管可以被配置为在电插入器的第一表面和/或弹性介电体之间提供多个电连接，以及电插入器和/或弹性介电体的第二相对的表面。 本文公开的系统和方法可以提供弹性电插入器的改进的垂直顺应性，改进的接触力控制和/或改进的尺寸稳定性。

公开(公告)号：US20140186145A1

公开(公告)日：2014-07-03

申请号：US14141812

申请日：2013-12-27

Applicant: Cascade Microtech, Inc.

Inventor： Frank Fehrmann ,  Botho Hirschfeld ,  Stojan Kanev

IPC: H01L21/67

CPC classification number: H01L21/67745 ,  H01L21/67775

Abstract: Systems and methods for providing wafer access in a wafer processing system are disclosed herein. The methods may include docking a first wafer cassette on the wafer processing system and removing a selected wafer from the first wafer cassette with the wafer processing system. The methods further may include performing a process operation on the selected wafer with the wafer processing system and undocking the first wafer cassette from the wafer processing system while performing the process operation. The methods also may include docking a second wafer cassette (which may be the same as or different from the first wafer cassette) on the wafer processing system, inventorying the second wafer cassette with the wafer processing system, and/or subsequently placing the selected wafer in the second wafer cassette. The systems may include wafer processing systems that include a controller that is programmed to perform at least a portion of the methods.

Abstract translation: 本文公开了在晶片处理系统中提供晶片访问的系统和方法。 所述方法可以包括将晶片处理系统上的第一晶片盒对接，并且利用晶片处理系统从第一晶片盒移除选定的晶片。 该方法还可以包括使用晶片处理系统在所选择的晶片上执行处理操作，并且在执行处理操作时从晶片处理系统脱离第一晶片盒。 所述方法还可以包括将第二晶片盒（其可以与第一晶片盒相同或不同）对准在晶片处理系统上，利用晶片处理系统盘存第二晶片盒，和/或随后将所选择的晶片 在第二晶片盒中。 系统可以包括晶片处理系统，其包括被编程为执行方法的至少一部分的控制器。