公开(公告)号：US10134753B2

公开(公告)日：2018-11-20

申请号：US15455900

申请日：2017-03-10

Applicant: Chang-Hyun Lee

Inventor： Chang-Hyun Lee

IPC: H01L27/115 ,  H01L27/11582 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66 ,  H01L29/792

Abstract: According to example embodiments, a vertical memory device includes a low resistance layer on a lower insulation layer, a channel layer on the low resistance layer, a plurality of vertical channels on the channel layer, and a plurality of gate lines. The vertical channels extend in a first direction that is perpendicular with respect to a top surface of the channel layer. The gate lines surround outer sidewalls of the vertical channels, and are stacked in the first direction and are spaced apart from each other.

公开(公告)号：US09640549B2

公开(公告)日：2017-05-02

申请号：US14534181

申请日：2014-11-06

Applicant: Seok-Won Lee ,  Joon-Hee Lee ,  Dong-Seog Eun ,  Chang-Hyun Lee

Inventor： Seok-Won Lee ,  Joon-Hee Lee ,  Dong-Seog Eun ,  Chang-Hyun Lee

IPC: H01L27/115 ,  H01L27/11582 ,  H01L27/11556 ,  G11C5/06 ,  H01L27/11548 ,  H01L27/11575 ,  G11C8/14 ,  H01L29/66 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11582 ,  G11C5/063 ,  G11C8/14 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A vertical memory device includes a substrate, a channel, gate lines and a connecting portion. A plurality of the channels extend in a first direction which is vertical to a top surface of a substrate. A plurality of the gate lines are stacked in the first direction to be spaced apart from each other and extend in a second, lengthwise direction, each gate line intersecting a set of channels and surrounding outer sidewalls of each channel of the set of channels. The gate lines forms a stepped structure which includes a plurality of vertical levels. A connecting portion connects a group of gate lines of the plurality of gate lines located at the same vertical level, the connecting portion diverging from the second direction in which the gate lines of the group of gate lines extend.

公开(公告)号：US09443596B2

公开(公告)日：2016-09-13

申请号：US14192544

申请日：2014-02-27

Applicant: Chang-Hyun Lee

Inventor： Chang-Hyun Lee

IPC: G11C11/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/30 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/30 ,  G11C16/3427

Abstract: A non-volatile memory device includes a memory cell array and a voltage generator. The memory cell array has a plurality of cell strings in which a plurality of memory cells are connected with each other in series between a string select transistor and a ground select transistor. The voltage generator generates a program voltage, a first pass voltage, and a second pass voltage. A first boost channel voltage applied when programming an outermost memory cell from among the memory cells of each of non-selected cell strings of the cell strings is lower than a second boost channel voltage applied when programming one of remaining memory cells except for the outermost memory cell. The non-volatile memory device prevents programming disturb caused by hot carrier injection.

Abstract translation: 非易失性存储器件包括存储单元阵列和电压发生器。 存储单元阵列具有多个单元串，其中多个存储单元串联连接在串选择晶体管和接地选择晶体管之间。 电压发生器产生编程电压，第一通过电压和第二通过电压。 当从单元串的未选择单元串中的每一个的存储器单元中编程最外层存储单元时施加的第一升压通道电压低于在编程除最外存储器之外的剩余存储单元之一时所应用的第二升压通道电压 细胞。 非易失性存储器件防止由热载流子注入引起的编程干扰。

公开(公告)号：US09406692B2

公开(公告)日：2016-08-02

申请号：US14588693

申请日：2015-01-02

Applicant: Chang-hyun Lee

Inventor： Chang-hyun Lee

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575

Abstract: A vertical-type nonvolatile memory device is provided in which differences between the sizes of channel holes in which channel structures are formed are reduced. The vertical-type nonvolatile memory device includes a substrate having channel hole recess regions in a surface thereof. Channel structures vertically protrude from the surface of the substrate on ones of the channel hole recess regions, and memory cell stacks including insulating and conductive layers are alternately stacked along sidewalls of the channel structures. A common source line extends along the surface of the substrate on other ones of the channel hole recess regions in a word line recess region, which separates adjacent memory cell stacks. Related fabrication methods are also discussed.

Abstract translation: 提供了一种垂直型非易失性存储装置，其中形成沟道结构的通道孔的尺寸之间的差异减小。 垂直型非易失性存储装置包括在其表面具有通道孔凹部区域的基板。 通道结构在通道孔凹陷区域中的一个上从衬底的表面垂直突出，并且包括绝缘和导电层的存储单元堆叠沿着沟道结构的侧壁交替堆叠。 公共源极线沿着衬底的表面延伸在字线凹槽区域中的通道孔凹槽区域中的另一个上，该区域分隔相邻的存储器单元堆叠。 还讨论了相关的制造方法。

公开(公告)号：US20150318293A1

公开(公告)日：2015-11-05

申请号：US14640784

申请日：2015-03-06

Applicant: Chang Hyun LEE ,  Jin-Kyu KIM

Inventor： Chang Hyun LEE ,  Jin-Kyu KIM

IPC: H01L27/115

CPC classification number: H01L27/11556 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11541 ,  H01L27/11573

Abstract: A non-volatile memory device including a cell array area including a plurality of memory cells and word lines and bit lines, which are connected to the plurality of memory cells, a core circuit area including a page buffer circuit and a row decoder circuit, the pager buffer circuit configured to temporarily store data input to and output from the plurality of memory cells, and the row decoder circuit configured to select some of the word lines corresponding to an address input thereto, and an input/output circuit area including a data input/output buffer circuit, the data input/output buffer circuit configured to at least one of transmit data to the page buffer circuit and receive data from the page buffer circuit, and the input/output circuit area including at least one asymmetrical transistor having a source region and a drain region asymmetrically disposed with respect to the gate structure may be provided.

Abstract translation: 一种非易失性存储器件，包括连接到多个存储器单元的包括多个存储器单元和字线和位线的单元阵列区域，包括页缓冲器电路和行解码器电路的核心电路区域， 寻呼缓冲电路，被配置为临时存储输入到多个存储单元并从多个存储单元输出的数据;以及行解码器电路，被配置为选择与输入的地址对应的一些字线，以及包括数据输入的输入/输出电路区 /输出缓冲器电路，数据输入/输出缓冲电路被配置为发送数据到页缓冲器电路中的至少一个并从页缓冲器电路接收数据，并且输入/输出电路区域包括至少一个不对称晶体管，源极 区域和相对于栅极结构不对称地设置的漏极区域。

公开(公告)号：US09130524B2

公开(公告)日：2015-09-08

申请号：US14347634

申请日：2011-11-07

Applicant: Jong Hoon Park ,  Chang Hyun Lee ,  Chang Kun Park

Inventor： Jong Hoon Park ,  Chang Hyun Lee ,  Chang Kun Park

IPC: H03F3/04 ,  H03G3/00 ,  H03F1/22 ,  H03F1/32 ,  H03F3/21 ,  H03F3/193 ,  H03F1/02 ,  H03F3/195

CPC classification number: H03G3/00 ,  H03F1/0266 ,  H03F1/223 ,  H03F1/3205 ,  H03F3/193 ,  H03F3/195 ,  H03F3/211 ,  H03F2200/18 ,  H03F2200/451 ,  H03F2203/21106 ,  H03F2203/21112 ,  H03F2203/21142

Abstract: Disclosed is a linear amplifier which includes: a common source transistor with the gate connected with an input node; a first common gate transistor connected with the common source transistor in a cascode type, with the drain connected with an output node; and a second common gate transistor connected in parallel with the first common gate transistor, with the gate connected with the input node and the drain connected with the output node.

Abstract translation: 公开了一种线性放大器，其包括：公共源晶体管，其栅极与输入节点连接; 与共源共栅型公共源晶体管连接的第一公共栅极晶体管，漏极与输出节点连接; 以及与所述第一公共栅极晶体管并联连接的第二公共栅极晶体管，所述栅极与所述输入节点连接，所述漏极与所述输出节点连接。

公开(公告)号：US20150137216A1

公开(公告)日：2015-05-21

申请号：US14534181

申请日：2014-11-06

Applicant: Seok-Won LEE ,  Joon-Hee LEE ,  Dong-Seog EUN ,  Chang-Hyun LEE

Inventor： Seok-Won LEE ,  Joon-Hee LEE ,  Dong-Seog EUN ,  Chang-Hyun LEE

IPC: H01L27/115 ,  G11C5/06

CPC classification number: H01L27/11582 ,  G11C5/063 ,  G11C8/14 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

Abstract: A vertical memory device includes a substrate, a channel, gate lines and a connecting portion. A plurality of the channels extend in a first direction which is vertical to a top surface of a substrate. A plurality of the gate lines are stacked in the first direction to be spaced apart from each other and extend in a second, lengthwise direction, each gate line intersecting a set of channels and surrounding outer sidewalls of each channel of the set of channels. The gate lines forms a stepped structure which includes a plurality of vertical levels. A connecting portion connects a group of gate lines of the plurality of gate lines located at the same vertical level, the connecting portion diverging from the second direction in which the gate lines of the group of gate lines extend.

Abstract translation: 垂直存储器件包括衬底，通道，栅极线和连接部分。 多个通道在与基板的顶表面垂直的第一方向上延伸。 多个栅极线在第一方向上被堆叠以彼此间隔开并且在第二长度方向上延伸，每个栅极线与通道组的每组通道的每个通道的外侧壁相交。 栅极线形成包括多个垂直电平的阶梯结构。 连接部分连接位于相同垂直高度的多条栅极线的一组栅极线，该连接部分从栅极线组的栅极线延伸的第二方向发散。

公开(公告)号：US20140264549A1

公开(公告)日：2014-09-18

申请号：US14191568

申请日：2014-02-27

Applicant: Chang-Hyun Lee

Inventor： Chang-Hyun Lee

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/04 ,  H01L29/16 ,  H01L29/66833 ,  H01L29/7926

Abstract: A vertical memory device includes a substrate, a column of vertical channels on the substrate and spaced apart along a direction parallel to the substrate, respective charge storage structures on sidewalls of respective ones of the vertical channels and gate electrodes vertically spaced along the charge storage structures. The vertical memory device further includes an isolation pattern disposed adjacent the column of vertical channels and including vertical extension portions extending parallel to the vertical channels and connection portions extending between adjacent ones of the vertical extension portions.

Abstract translation: 垂直存储器件包括衬底，衬底上的垂直通道列，并沿着平行于衬底的方向间隔开，相应的垂直通道的侧壁上的电荷存储结构和沿着电荷存储结构垂直间隔开的栅电极 。 垂直存储装置还包括邻近垂直通道列布置的隔离图案，并且包括平行于垂直通道延伸的垂直延伸部分和在相邻的垂直延伸部分之间延伸的连接部分。

公开(公告)号：US20140264548A1

公开(公告)日：2014-09-18

申请号：US14176332

申请日：2014-02-10

Applicant: Chang-Hyun Lee ,  Hyun-Jung Kim ,  Dong-Hoon Jang ,  Albert Fayrushin

Inventor： Chang-Hyun Lee ,  Hyun-Jung Kim ,  Dong-Hoon Jang ,  Albert Fayrushin

IPC: H01L27/115

CPC classification number: H01L27/11582 ,  H01L21/76224 ,  H01L27/11551 ,  H01L27/11565 ,  H01L29/7889

Abstract: A memory device may include a plurality of semiconductor patterns on a substrate including a plurality of first impurity regions doped at a first impurity concentration, a plurality of second impurity regions at portions of the substrate contacting the plurality of semiconductor patterns and doped at a second impurity concentration, a plurality of channel patterns on the plurality of semiconductor patterns, a plurality of gate structures, a plurality of third impurity regions at portions of the substrate adjacent to end portions of the plurality of gate structures, and a plurality of fourth impurity regions at portions of the substrate between the second and third impurity regions and between adjacent second impurity regions. The plurality of fourth impurity regions may be doped at a third impurity concentration which may be lower than the first and second impurity concentrations.

Abstract translation: 存储器件可以包括在衬底上的多个半导体图案，其包括以第一杂质浓度掺杂的多个第一杂质区域，在与多个半导体图案接触并且以第二杂质掺杂的衬底的部分处的多个第二杂质区域 浓度，多个半导体图案上的多个沟道图案，多个栅极结构，在与多个栅极结构的端部相邻的基板的部分处的多个第三杂质区域，以及多个第四杂质区域 在第二和第三杂质区之间和相邻的第二杂质区之间的衬底的部分。 可以在可以低于第一和第二杂质浓度的第三杂质浓度下掺杂多个第四杂质区域。

公开(公告)号：US08427883B2

公开(公告)日：2013-04-23

申请号：US12980788

申请日：2010-12-29

Applicant: Dae-Suk Kim ,  Chang-Hyun Lee

Inventor： Dae-Suk Kim ,  Chang-Hyun Lee

IPC: G11C7/10

CPC classification number: G11C7/1078 ,  G11C7/109 ,  G11C29/46

Abstract: A setting circuit includes a selection unit configured to select one of a predefined code and an external code in response to a test signal, and a setting information generation unit configured to generate setting information in response to the code selected by the selection unit.

Abstract translation: 设置电路包括：响应于测试信号选择预定码和外部码之一的选择单元;以及设置信息生成单元，用于响应于由选择单元选择的代码生成设置信息。