公开(公告)号：US08406058B2

公开(公告)日：2013-03-26

申请号：US12983985

申请日：2011-01-04

Applicant: Ching-Wei Wu ,  Cheng-Hung Lee ,  He-Zhou Wan ,  Wei-Yang Jiang

Inventor： Ching-Wei Wu ,  Cheng-Hung Lee ,  He-Zhou Wan ,  Wei-Yang Jiang

IPC: G11C11/34

CPC classification number: G11C8/08 ,  G11C17/14

Abstract: A read only memory (ROM) and an operating method thereof are provided. The read only memory includes: a control circuit, powered by a first power source for outputting a control signal within a first voltage range; a voltage shifter, for expanding the amplitude of the control signal to a second voltage range; a word line driver, powered by a second power source with a voltage which is higher than that of the first power source, for driving one of a plurality of word lines of a read only memory cell array according to the control signal which is expanded to be within the second voltage range; and an input/output circuit, for connecting the plurality of bit lines to read out messages.

Abstract translation: 提供只读存储器（ROM）及其操作方法。 只读存储器包括：控制电路，由第一电源供电，用于在第一电压范围内输出控制信号; 电压移位器，用于将控制信号的振幅扩大到第二电压范围; 由具有比第一电源的电压高的第二电源供电的字线驱动器，用于根据扩展至的只读存储单元阵列的多个字线中的一个字线驱动 处于第二电压范围内; 以及用于连接多个位线以读出消息的输入/输出电路。

公开(公告)号：US08399961B2

公开(公告)日：2013-03-19

申请号：US12974896

申请日：2010-12-21

Applicant: Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Cheng Hung Lee ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Min-Chie Jeng

Inventor： Hsiao-Tsung Yen ,  Yu-Ling Lin ,  Cheng Hung Lee ,  Chin-Wei Kuo ,  Ho-Hsiang Chen ,  Min-Chie Jeng

IPC: H01L27/08

CPC classification number: H01L23/60 ,  H01L23/66 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L27/0248 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05073 ,  H01L2224/05147 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/05655 ,  H01L2224/13083 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14131 ,  H01L2224/16145 ,  H01L2224/16148 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/17517 ,  H01L2224/81455 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/131 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00

Abstract: A device includes a die including a main circuit and a first pad coupled to the main circuit. A work piece including a second pad is bonded to the die. A first plurality of micro-bumps is electrically coupled in series between the first and the second pads. Each of the plurality of micro-bumps includes a first end joining the die and a second end joining the work piece. A micro-bump is bonded to the die and the work piece. The second pad is electrically coupled to the micro-bump.

Abstract translation: 一种器件包括：裸片，包括主电路和耦合到主电路的第一焊盘。 包括第二垫的工件被结合到模具。 第一多个微凸块在第一和第二焊盘之间串联电耦合。 多个微型凸块中的每一个包括连接模具的第一端和连接工件的第二端。 微凸块与模具和工件结合。 第二焊盘电耦合到微凸起。

公开(公告)号：US20130003446A1

公开(公告)日：2013-01-03

申请号：US13616377

申请日：2012-09-14

Applicant: Hsu-Shun Chen ,  Cheng-Hung Lee ,  Hong-Chen Cheng ,  Chung-Yi Wu

Inventor： Hsu-Shun Chen ,  Cheng-Hung Lee ,  Hong-Chen Cheng ,  Chung-Yi Wu

IPC: G11C5/14 ,  G11C11/00

CPC classification number: G11C8/08 ,  G11C11/413

Abstract: An integrated circuit includes a positive power supply node, a current tracking circuit, and a current mirroring circuit including a plurality of current paths coupled in parallel. The currents of the plurality of current paths mirror a current of the current tracking circuit. The current mirroring circuit is configured to turn off the plurality of current paths one-by-one in response to a reduction in a positive power supply voltage on the positive power supply node. The integrated circuit further includes a charging node receiving a summation current of the plurality of current paths, wherein a voltage on the charging node is configured to increase through a charging of the summation current.

Abstract translation: 集成电路包括正电源节点，电流跟踪电路和包括并联耦合的多个电流路径的电流镜像电路。 多个电流通路的电流反映了电流跟踪电路的电流。 电流镜像电路被配置为响应于正电源节点上的正电源电压的减小而逐个关闭多个电流路径。 集成电路还包括接收多个电流路径的求和电流的充电节点，其中充电节点上的电压被配置为通过对和电流的充电而增加。

公开(公告)号：US08305791B2

公开(公告)日：2012-11-06

申请号：US12784133

申请日：2010-05-20

Applicant: Ching-Wei Wu ,  Cheng Hung Lee ,  Li-Chen Chen ,  Weiyang Jiang

Inventor： Ching-Wei Wu ,  Cheng Hung Lee ,  Li-Chen Chen ,  Weiyang Jiang

IPC: G11C17/00

CPC classification number: G11C17/10 ,  H01L27/112

Abstract: A memory circuit includes a plurality of bit lines. A first memory cell and a second memory cell are coupled in series. Each of the first memory cell and the second memory cell is capable of storing a first type datum. The first memory cell and the second memory cell share a first common source/drain (S/D) region. The first common S/D region is electrically isolated from all of the bit lines.

Abstract translation: 存储电路包括多个位线。 第一存储单元和第二存储单元串联耦合。 第一存储单元和第二存储单元中的每一个能够存储第一类型的数据。 第一存储单元和第二存储单元共享第一公共源极/漏极（S / D）区域。 第一公共S / D区域与所有位线电隔离。

公开(公告)号：US08289754B2

公开(公告)日：2012-10-16

申请号：US12877695

申请日：2010-09-08

Applicant: Cheng Hung Lee ,  Hung-Jen Liao

Inventor： Cheng Hung Lee ,  Hung-Jen Liao

IPC: G11C11/00

CPC classification number: G11C11/412

Abstract: A static random access memory (SRAM) cell includes a pair of cross-coupled inverters having a first node and a second node. A first transistor is coupled between the first node and a first bit line. A second transistor is coupled between the second node and a second bit line. A third transistor is coupled with the first node. The third transistor has a threshold voltage that is higher than that of a fourth transistor of the pair of cross-coupled inverters by about 10% or more. A fifth transistor is coupled between the third transistor and a third bit line.

Abstract translation: 静态随机存取存储器（SRAM）单元包括具有第一节点和第二节点的一对交叉耦合的反相器。 第一晶体管耦合在第一节点和第一位线之间。 第二晶体管耦合在第二节点和第二位线之间。 第三晶体管与第一节点耦合。 第三晶体管具有比该对交叉耦合的反相器对的第四晶体管的阈值电压高约10％以上的阈值电压。 第五晶体管耦合在第三晶体管和第三位线之间。

公开(公告)号：US08217430B2

公开(公告)日：2012-07-10

申请号：US12786003

申请日：2010-05-24

Applicant: Cheng Hung Lee

Inventor： Cheng Hung Lee

IPC: H01L27/10

CPC classification number: H01L27/0207 ,  H01L27/105

Abstract: An integrated circuit (IC) chip includes a first memory cell array block having a first metal layer containing at least two power lines, and a second memory cell array block containing at least two power lines independent of each other, wherein all the power lines on the first metal layer serving the first memory cell array block do not extend into the second memory cell array block, and all the power lines on the first metal layer serving the second memory cell array block do not extend into the first memory cell array block.

Abstract translation: 集成电路（IC）芯片包括具有包含至少两条电源线的第一金属层的第一存储单元阵列块和包含彼此独立的至少两条电源线的第二存储单元阵列块，其中所有电源线在 服务于第一存储单元阵列块的第一金属层不延伸到第二存储单元阵列块中，并且服务于第二存储单元阵列块的第一金属层上的所有电力线不延伸到第一存储单元阵列块中。

公开(公告)号：US20120147688A1

公开(公告)日：2012-06-14

申请号：US13397102

申请日：2012-02-15

Applicant: Yen-Huei CHEN ,  Cheng Hung LEE

Inventor： Yen-Huei CHEN ,  Cheng Hung LEE

IPC: G11C5/14

CPC classification number: G11C11/413 ,  G11C11/412

Abstract: An integrated circuit includes at least one memory array for storing data. A first switch is coupled with the memory array. A first power line is coupled with the first switch. The first power line is operable to supply a first power voltage. A second switch is coupled with the memory array. A second power line is coupled with the second switch. The second power line is operable to supply a second power voltage for retaining the data during a retention mode. A third power line is coupled with the memory array. The third power line is capable of providing a third power voltage.

Abstract translation: 集成电路包括用于存储数据的至少一个存储器阵列。 第一开关与存储器阵列耦合。 第一电力线与第一开关耦合。 第一电力线可操作以提供第一电力电压。 第二开关与存储器阵列耦合。 第二电源线与第二开关耦合。 第二电源线可操作以在保持模式期间提供用于保留数据的第二电源电压。 第三电源线与存储器阵列耦合。 第三电源线能够提供第三电源电压。

公开(公告)号：US20120014158A1

公开(公告)日：2012-01-19

申请号：US12838572

申请日：2010-07-19

Applicant: Ching-Wei WU ,  Cheng Hung LEE ,  Kuang Ting CHEN

Inventor： Ching-Wei WU ,  Cheng Hung LEE ,  Kuang Ting CHEN

IPC: G11C17/12

CPC classification number: G11C17/12

Abstract: A memory device includes an array of transistors, a plurality of bit lines, and a plurality of source lines. The transistors include gate, drain and source terminals. The gate terminals are electrically coupled to word lines. The plurality of bit lines connect a power source to the drain terminals of the array of transistors and the plurality of source lines connect the power source to the source terminals of the array of transistors. The connections are made active during a standby mode, thereby limiting leakage current without entailing drawbacks associated with degraded memory access/cycle time.

Abstract translation: 存储器件包括晶体管阵列，多个位线和多条源极线。 晶体管包括栅极，漏极和源极端子。 栅极端子电耦合到字线。 多个位线将电源连接到晶体管阵列的漏极端子，并且多个源极线将电源连接到晶体管阵列的源极端子。 在待机模式期间，这些连接被激活，从而限制泄漏电流，而不会引起与存储器访问/周期时间下降有关的缺点。

公开(公告)号：US08050082B2

公开(公告)日：2011-11-01

申请号：US12259009

申请日：2008-10-27

Applicant: Cheng Hung Lee

Inventor： Cheng Hung Lee

IPC: G11C11/00

CPC classification number: G11C11/412

Abstract: An integrated circuit device includes a first word-line; a second word-line; a first bit-line; and a static random access memory (SRAM) cell. The SRAM cell includes a storage node; a pull-up transistor having a source/drain region coupled to the storage node; a pull-down transistor having a source/drain region coupled to the storage node; a first pass-gate transistor comprising a gate coupled to the first word-line; and a second pass-gate transistor including a gate coupled to the second word-line. Each of the first and the second pass-gate transistors includes a first source/drain region coupled to the first bit-line, and a second source/drain region coupled to the storage node.

Abstract translation: 集成电路装置包括第一字线; 第二个字线; 第一个位线 和静态随机存取存储器（SRAM）单元。 SRAM单元包括存储节点; 具有耦合到存储节点的源极/漏极区域的上拉晶体管; 具有耦合到存储节点的源极/漏极区域的下拉晶体管; 第一通过栅晶体管，包括耦合到第一字线的栅极; 以及包括耦合到第二字线的栅极的第二栅极晶体管。 第一和第二栅极晶体管中的每一个包括耦合到第一位线的第一源极/漏极区域和耦合到存储节点的第二源极/漏极区域。

公开(公告)号：US20110158007A1

公开(公告)日：2011-06-30

申请号：US12708923

申请日：2010-02-19

Applicant: Hsu-Shun Chen ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Chung-Yi Wu ,  Chih-Chieh Chiu

Inventor： Hsu-Shun Chen ,  Cheng Hung Lee ,  Chung-Ji Lu ,  Hong-Chen Cheng ,  Chung-Yi Wu ,  Chih-Chieh Chiu

IPC: G11C7/00 ,  G11C5/14

CPC classification number: G11C7/1048 ,  G11C5/14

Abstract: In some embodiments related to a memory array, a sense amplifier (SA) uses a first power supply, e.g., voltage VDDA, while other circuitry, e.g., signal output logic, uses a second power supply, e.g., voltage VDDB. Various embodiments place the SA and a pair of transferring devices at a local IO row, and a voltage keeper at the main IO section of the same memory array. The SA, the transferring devices, and the voltage keeper, when appropriate, operate together so that the data logic of the circuitry provided by voltage VDDB is the same as the data logic of the circuitry provided by voltage VDDA.

Abstract translation: 在与存储器阵列相关的一些实施例中，读出放大器（SA）使用第一电源，例如电压VDDA，而其它电路（例如，信号输出逻辑）使用第二电源，例如电压VDDB。 各种实施例将SA和一对传送装置放置在本地IO行上，并将电压保持器放置在同一存储器阵列的主IO部分。 SA，传输装置和电压保持器在适当的情况下一起工作，使得由电压VDDB提供的电路的数据逻辑与由电压VDDA提供的电路的数据逻辑相同。