公开(公告)号：US08748888B2

公开(公告)日：2014-06-10

申请号：US12648680

申请日：2009-12-29

Applicant: Jeong Woo Lee ,  Hyung Dong Lee ,  Jun Gi Choi ,  Sang Hoon Shin ,  Xiang Hua Cui

Inventor： Jeong Woo Lee ,  Hyung Dong Lee ,  Jun Gi Choi ,  Sang Hoon Shin ,  Xiang Hua Cui

IPC: H01L23/58

CPC classification number: H01L25/0657 ,  G01R31/2884 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor integrated circuit includes a multi-chip package having a plurality of semiconductor chips. The semiconductor integrated circuit includes a signal line; and a signal loading compensation section in a semiconductor chip among the plurality of semiconductor chips, configured to apply a designed signal loading to the signal line in response to activation of a test signal. Here, the designed signal loading has a value corresponding to a signal loading component of another semiconductor chip among the plurality of semiconductor chips to the signal line.

Abstract translation: 半导体集成电路包括具有多个半导体芯片的多芯片封装。 半导体集成电路包括信号线; 以及多个半导体芯片中的半导体芯片中的信号负载补偿部，被配置为响应于测试信号的激活而将设计的信号加载到信号线。 这里，设计的信号负载具有与信号线的多个半导体芯片中的另一半导体芯片的信号负载分量相对应的值。

公开(公告)号：US08698276B2

公开(公告)日：2014-04-15

申请号：US13338716

申请日：2011-12-28

Applicant: Jeong-Woo Lee ,  Hyung-Dong Lee ,  Sang-Hoon Shin ,  Hyang-Hwa Choi

Inventor： Jeong-Woo Lee ,  Hyung-Dong Lee ,  Sang-Hoon Shin ,  Hyang-Hwa Choi

IPC: H01L23/52

CPC classification number: H01L22/22 ,  G01R31/2853 ,  H01L23/481 ,  H01L23/5258 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2225/06596 ,  H01L2924/3011

Abstract: A semiconductor system includes a controller; a semiconductor device comprising a plurality of stacked semiconductor chips stacked over the controller, and a plurality of through-silicon vias (TSVs) configured to commonly transfer a signal to the plurality of stacked semiconductor chips; and a defect information transfer TSV configured to transfer TSV defect information sequentially outputted from at least one of the semiconductor chips to the controller, wherein the controller comprises: a plurality of first repair fuse units configured to set first fuse information based on the TSV defect information; and a plurality of first TSV selection units configured to selectively drive the TSVs in response to the first fuse information.

Abstract translation: 半导体系统包括控制器; 包括堆叠在所述控制器上的多个层叠半导体芯片的半导体器件以及被配置为共同地将信号传送到所述多个堆叠的半导体芯片的多个穿硅通孔（TSV） 以及缺陷信息传送TSV，被配置为将从半导体芯片中的至少一个依次输出的TSV缺陷信息传送到控制器，其中，所述控制器包括：多个第一修复熔丝单元，被配置为基于所述TSV缺陷信息来设置第一熔丝信息 ; 以及多个第一TSV选择单元，被配置为响应于所述第一熔丝信息选择性地驱动所述TSV。

公开(公告)号：US08310062B2

公开(公告)日：2012-11-13

申请号：US12346429

申请日：2008-12-30

Applicant: Jun-Ho Lee ,  Hyung-Dong Lee ,  Hyun-Seok Kim

Inventor： Jun-Ho Lee ,  Hyung-Dong Lee ,  Hyun-Seok Kim

IPC: H01L23/552 ,  H01L23/02

CPC classification number: H01L23/552 ,  H01L23/3128 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2224/32225 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor package includes a wire board, a plurality of semiconductor chips configured to be stacked over the wire board and to be electrically coupled with the wire board, and at least one shielding unit configured to be formed between the plurality of semiconductor chips and to be maintained at a predetermined voltage.

Abstract translation: 一种半导体封装，包括线路板，多个半导体芯片，被配置为堆叠在线路板上并与线路板电连接;以及至少一个屏蔽单元，被配置为形成在所述多个半导体芯片之间， 保持在预定电压。

公开(公告)号：US20120213022A1

公开(公告)日：2012-08-23

申请号：US13399643

申请日：2012-02-17

Applicant: Hyung Gyun YANG ,  Hyung Dong LEE ,  Yong Kee KWON ,  Young Suk MOON ,  Sung Wook KIM ,  Keun Hyung KIM

Inventor： Hyung Gyun YANG ,  Hyung Dong LEE ,  Yong Kee KWON ,  Young Suk MOON ,  Sung Wook KIM ,  Keun Hyung KIM

IPC: G11C29/00

CPC classification number: G11C29/48 ,  G11C2029/0401

Abstract: A system in package (SIP) semiconductor system includes a memory device, a controller, a first input/output terminal, a test control unit, and a second input/output terminal. The controller communicates with the memory device. The first input/output terminal performs communication between the controller and a device external to the SIP semiconductor system. The test control unit controls a predetermined test mode of the memory device. The second input/output terminal performs communication between the test control unit and at least the device external to the SIP semiconductor system.

Abstract translation: 封装（SIP）半导体系统包括存储器件，控制器，第一输入/输出端子，测试控制单元和第二输入/输出端子。 控制器与存储器件通信。 第一输入/输出端子执行控制器与SIP半导体系统外部的设备之间的通信。 测试控制单元控制存储器件的预定测试模式。 第二输入/输出端子执行测试控制单元与至少在SIP半导体系统外部的设备之间的通信。

公开(公告)号：US20120140584A1

公开(公告)日：2012-06-07

申请号：US13219656

申请日：2011-08-27

Applicant: Yong Kee KWON ,  Hyung Dong LEE ,  Young Suk MOON ,  Hyung Gyun YANG ,  Sung Wook KIM

Inventor： Yong Kee KWON ,  Hyung Dong LEE ,  Young Suk MOON ,  Hyung Gyun YANG ,  Sung Wook KIM

IPC: G11C8/18

CPC classification number: G11C7/22 ,  G06F2213/0038 ,  G11C7/1063 ,  G11C7/1066 ,  G11C7/222 ,  G11C11/22

Abstract: A semiconductor system, a semiconductor memory apparatus, and a method for input/output of data using the same are disclosed. The semiconductor system includes a controller and a memory apparatus where the controller is configured to transmit a clock signal, a data output command, an address signal, and a second strobe signal to a memory apparatus. The memory apparatus is configured to provide data to the controller in synchronization with the second strobe signal, and in response to the clock signal, the data output command, the address signal, and the second strobe signal received from the controller.

Abstract translation: 公开了一种半导体系统，半导体存储装置和使用其的数据的输入/输出方法。 半导体系统包括控制器和存储装置，其中控制器被配置为向存储装置发送时钟信号，数据输出命令，地址信号和第二选通信号。 存储装置被配置为与第二选通信号同步地向控制器提供数据，并且响应于从控制器接收到的时钟信号，数据输出命令，地址信号和第二选通信号。

公开(公告)号：US08171358B2

公开(公告)日：2012-05-01

申请号：US12614672

申请日：2009-11-09

Applicant: Sang-Hoon Shin ,  Hyung-Dong Lee ,  Jeong-Woo Lee ,  Hyang-Hwa Choi

Inventor： Sang-Hoon Shin ,  Hyung-Dong Lee ,  Jeong-Woo Lee ,  Hyang-Hwa Choi

IPC: G01R31/28 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L22/22 ,  H01L23/481 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/3011

Abstract: A semiconductor device and a method for driving the same rapidly detect failure of a through-semiconductor-chip via and effectively repairing the failure using a latching unit assigned to each through-semiconductor-chip via. The semiconductor device includes a plurality of semiconductor chips that are stacked, and a plurality of through-semiconductor-chip vias to commonly transfer a signal to the plurality of semiconductor chips, wherein each of the semiconductor chips includes a multiplicity of latching units assigned to the through-semiconductor-chip vias and the multiplicity of latching units of each of the semiconductor chips constructs a boundary scan path including the plurality of through-semiconductor-chip vias to sequentially transfer test data.

Abstract translation: 半导体器件及其驱动方法可以快速检测半导体芯片通孔的故障，并使用分配给每个贯通半导体芯片通孔的锁存单元有效地修复故障。 半导体器件包括堆叠的多个半导体芯片，以及多个贯穿半导体芯片通孔，以共同地将信号传递到多个半导体芯片，其中每个半导体芯片包括分配给多个半导体芯片的多个锁存单元 通过半导体芯片通孔，并且每个半导体芯片的多个锁存单元构成包括多个通过半导体芯片通孔的边界扫描路径以顺序地传送测试数据。

公开(公告)号：US08154019B2

公开(公告)日：2012-04-10

申请号：US12649193

申请日：2009-12-29

Applicant: Yong Kee Kwon ,  Hyung Dong Lee ,  Young Park Kim

Inventor： Yong Kee Kwon ,  Hyung Dong Lee ,  Young Park Kim

IPC: H01L23/58

CPC classification number: G11C11/4074 ,  G11C5/147 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

Abstract: A semiconductor apparatus includes a reference voltage generation unit, a comparison voltage generation unit, and a calibration unit. The reference voltage generation unit is disposed in a reference die and configured to generate a reference voltage. The comparison voltage generation unit is disposed in a die stacked on the reference die and configured to generate a comparison voltage in response to a calibration control signal. The calibration unit is configured to compare a level of the reference voltage with a level of the comparison voltage and generate the calibration control signal.

Abstract translation: 半导体装置包括参考电压产生单元，比较电压产生单元和校准单元。 参考电压产生单元设置在参考管芯中，并被配置为产生参考电压。 比较电压产生单元设置在堆叠在参考管芯上的管芯中，并被配置为响应校准控制信号产生比较电压。 校准单元被配置为将参考电压的电平与比较电压的电平进行比较并产生校准控制信号。

公开(公告)号：US20110272692A1

公开(公告)日：2011-11-10

申请号：US12980984

申请日：2010-12-29

Applicant: Kwon Whan HAN ,  Hyung Dong LEE

Inventor： Kwon Whan HAN ,  Hyung Dong LEE

IPC: H01L23/544 ,  H01L27/02 ,  H01L23/482 ,  H01L23/525

CPC classification number: H01L25/0657 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/42 ,  H01L23/481 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/15311 ,  H01L2924/16251 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A size variable semiconductor chip includes a semiconductor chip area formed with a circuit layer and at least one cutting area extending parallel to at least one side of the semiconductor chip area. A plurality of scribe line parts and a plurality of active parts alternately formed with each other in the cutting area.

Abstract translation: 尺寸可变半导体芯片包括形成有电路层的半导体芯片区域和平行于半导体芯片区域的至少一侧延伸的至少一个切割区域。 多个切割线部分和多个有源部分在切割区域中彼此交替地形成。

公开(公告)号：US07999579B2

公开(公告)日：2011-08-16

申请号：US12165154

申请日：2008-06-30

Applicant: Hyung-Dong Lee ,  Dong-Hwee Kim ,  Hwa-Yong Yang

Inventor： Hyung-Dong Lee ,  Dong-Hwee Kim ,  Hwa-Yong Yang

IPC: H03B1/00 ,  H03K3/00

CPC classification number: H03K19/018521 ,  G11C7/1051 ,  G11C7/1054 ,  G11C11/4093

Abstract: An output driver is applicable to two or more interface standards. The output driver includes a pre-driver configured to generate pull-up control signals and pull-down control signals according to a logic value of data to be output and a target resistance, and adjust slew rates of the pull-up control signals and the pull-down control signals according to operation modes, and a driver configured to output the data in response to the pull-up and pull-down control signals.

Abstract translation: 输出驱动器适用于两个或多个接口标准。 输出驱动器包括预驱动器，其被配置为根据要输出的数据的逻辑值和目标电阻产生上拉控制信号和下拉控制信号，并且调整上拉控制信号的转换速率和 根据操作模式的下拉控制信号，以及配置为响应于上拉和下拉控制信号输出数据的驱动器。

公开(公告)号：US20100246288A1

公开(公告)日：2010-09-30

申请号：US12797022

申请日：2010-06-09

Applicant: Hyung Dong Lee

Inventor： Hyung Dong Lee

IPC: G11C7/22

CPC classification number: H03K19/094

Abstract: A data output circuit of a semiconductor memory apparatus includes a pre-driver generating pull-up and down signals from driving rising and falling data in active periods of rising and falling clocks, respectively, in accordance with a state of an output enable signal. A main driver generates last output data to a common node from the pull-up and down signals. An assistant pre-driver generates an assistant drive signal, which is activated when the rising data disagrees with the falling data, in correspondence with inputs of the rising data, the falling data, the rising clock, the falling clock, and a pipe output control signal. An assistant main driver generates assistant last output data to the common node from the pull-up and down signals in accordance with a state of the assistant drive signal.

Abstract translation: 半导体存储装置的数据输出电路包括预驱动器，分别根据输出使能信号的状态产生上升沿和下降沿的有效周期中的驱动上升和下降数据的上拉和下拉信号。 主驱动器从上拉和下拉信号产生到公共节点的最后输出数据。 辅助预驱动器产生辅助驱动信号，当上升数据与下降数据不一致时，其与上升数据，下降数据，上升时钟，下降时钟和管道输出控制的输入相对应地被激活 信号。 辅助主驱动器根据辅助驱动信号的状态从上拉和下拉信号产生辅助上一个输出数据到公共节点。