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    Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip packages are mounted
    53.
    发明授权
    Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip packages are mounted 失效
    具有镜像结构和双列直插存储器模块的堆叠板上芯片封装，其上安装有堆叠板上芯片封装

    公开(公告)号：US07276786B2

    公开(公告)日：2007-10-02

    申请号：US11177736

    申请日：2005-07-08

    Applicant: Jeong-Hyeon Cho ,  Jung-Joon Lee ,  Do-Hyung Kim ,  Byung-Se So

    Inventor： Jeong-Hyeon Cho ,  Jung-Joon Lee ,  Do-Hyung Kim ,  Byung-Se So

    IPC: H01L23/42 ,  H01L23/58 ,  H01L29/40

    CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L25/16 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/00014

    Abstract: Embodiments of the invention include a stacked board-on-chip (BOC) package having a mirroring structure and a dual inline memory module (DIMM) on which the stacked BOC package is mounted. A bottom surface of a first semiconductor chip faces a bottom surface of a second semiconductor chip. An interposer electrically connects first and second packages, respectively comprising the first and second semiconductor chips, to each other. The DIMM is obtained by electrically connecting BOC packages to each other on upper and lower substrates of a printed circuit board. Since a height of the stacked BOC packages is greater than a height of a conventional stacked BOC package, the DIMM has a minimum stub length and an optimal topology. Hence, the DIMM can have a signal with excellent fidelity by reducing a load upon a signal line, and installation or wiring of components within the DIMM 300 requires less effort.

    Abstract translation: 本发明的实施例包括具有镜像结构的堆叠板上芯片（BOC）封装和其上安装有堆叠的BOC封装的双列直插存储器模块（DIMM）。 第一半导体芯片的底面朝向第二半导体芯片的底面。 插入器将分别包括第一和第二半导体芯片的第一和第二封装彼此电连接。 通过在印刷电路板的上下基板上将BOC封装彼此电连接来获得DIMM。 由于堆叠的BOC封装的高度大于常规堆叠BOC封装的高度，所以DIMM具有最小的短截线长度和最佳拓扑。 因此，通过减少信号线上的负载，DIMM可以具有出色的保真度的信号，并且DIMM 300内的组件的安装或接线需要较少的努力。

    Semiconductor memory device and memory system using same
    54.
    发明申请
    Semiconductor memory device and memory system using same 失效
    半导体存储器件和使用其的存储器系统

    公开(公告)号：US20060184755A1

    公开(公告)日：2006-08-17

    申请号：US11352009

    申请日：2006-02-11

    Applicant: Jung-Joon Lee

    Inventor： Jung-Joon Lee

    IPC: G06F13/00

    CPC classification number: G11C7/20 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C2207/2254

    Abstract: There is provided a semiconductor memory device and a memory system using the same. The semiconductor memory device includes an input data delay time adjustor for varying an input delay time, selecting one bit of a n-bit input data, delaying the selected one bit by the input delay time and outputting the delayed bit, in response to a control signal during an input data delay test operation; and an output data delay time adjustor for varying an output delay time, selecting one bit of a m-bit output data, delaying the selected one bit by the output delay time and outputting the delayed bit, in response to the control signal during an output data delay test operation, wherein the input data delay time adjustor is arranged for n-bit input data, and wherein the output data delay time adjustor is arranged for m-bit output data.

    Abstract translation: 提供了一种半导体存储器件和使用该半导体存储器件的存储器系统。 半导体存储器件包括用于改变输入延迟时间的输入数据延迟时间调节器，选择n位输入数据的一位，响应于控制将所选择的一位延迟输入延迟时间并输出延迟位 在输入数据延迟测试操作期间信号; 以及输出数据延迟时间调整器，用于改变输出延迟时间，选择m位输出数据的一位，响应于输出期间的控制信号，将所选择的一位延迟输出延迟时间并输出延迟位 数据延迟测试操作，其中输入数据延迟时间调节器被配置用于n位输入数据，并且其中输出数据延迟时间调整器被布置用于m位输出数据。

    Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip package are mounted
    55.
    发明申请
    Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip package are mounted 失效
    堆叠的片上芯片封装，具有镜像结构和双列直插存储器模块，其上安装有堆叠的片上芯片封装

    公开(公告)号：US20060055017A1

    公开(公告)日：2006-03-16

    申请号：US11177736

    申请日：2005-07-08

    Applicant: Jeong-Hyeon Cho ,  Jung-Joon Lee ,  Do-Hyung Kim ,  Byung-Se So

    Inventor： Jeong-Hyeon Cho ,  Jung-Joon Lee ,  Do-Hyung Kim ,  Byung-Se So

    IPC: H01L23/02

    CPC classification number: H01L25/105 ,  H01L23/3128 ,  H01L25/16 ,  H01L2224/06136 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2225/1094 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/19041 ,  H01L2924/00014

    Abstract: Embodiments of the invention include a stacked board-on-chip (BOC) package having a mirroring structure and a dual inline memory module (DIMM) on which the stacked BOC package is mounted. A bottom surface of a first semiconductor chip faces a bottom surface of a second semiconductor chip. An interposer electrically connects first and second packages, respectively comprising the first and second semiconductor chips, to each other. The DIMM is obtained by electrically connecting BOC packages to each other on upper and lower substrates of a printed circuit board. Since a height of the stacked BOC packages is greater than a height of a conventional stacked BOC package, the DIMM has a minimum stub length and an optimal topology. Hence, the DIMM can have a signal with excellent fidelity by reducing a load upon a signal line, and installation or wiring of components within the DIMM 300 requires less effort.

    Abstract translation: 本发明的实施例包括具有镜像结构的堆叠板上芯片（BOC）封装和其上安装有堆叠的BOC封装的双列直插存储器模块（DIMM）。 第一半导体芯片的底面朝向第二半导体芯片的底面。 插入器将分别包括第一和第二半导体芯片的第一和第二封装彼此电连接。 通过在印刷电路板的上下基板上将BOC封装彼此电连接来获得DIMM。 由于堆叠的BOC封装的高度大于常规堆叠BOC封装的高度，所以DIMM具有最小的短截线长度和最佳拓扑。 因此，通过减少信号线上的负载，DIMM可以具有出色的保真度的信号，并且DIMM 300内的组件的安装或接线需要较少的努力。

    Memory system with improved signal integrity
    56.
    发明申请
    Memory system with improved signal integrity 审中-公开
    具有改善信号完整性的存储系统

    公开(公告)号：US20050002241A1

    公开(公告)日：2005-01-06

    申请号：US10837610

    申请日：2004-05-04

    Applicant: Sung-Joo Park ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Chil-Nam Yoon

    Inventor： Sung-Joo Park ,  Byung-Se So ,  Jung-Joon Lee ,  Jae-Jun Lee ,  Chil-Nam Yoon

    IPC: G06F12/00 ,  G06F13/40 ,  G11C5/00 ,  G11C5/06

    CPC classification number: G06F13/4086

    Abstract: A memory system includes a memory controller, a memory bus connected to the memory controller, and a plurality of memory modules connected along the memory bus, where each of the memory modules includes a plurality of memory devices. The system also includes a dummy stub or a dummy module connected to the memory bus between the memory controller and the memory module closest to the memory controller among the plurality of memory modules. The dummy stub or dummy module improves a signal integrity of at least the memory module closest to the memory controller.

    Abstract translation: 存储器系统包括存储器控制器，连接到存储器控制器的存储器总线以及沿着存储器总线连接的多个存储器模块，其中每个存储器模块包括多个存储器件。 该系统还包括连接到存储器总线之间的存储器控​​制器和位于多个存储器模块中最靠近存储器控制器的存储器模块之间的虚拟存根或虚拟模块。 虚拟短线或虚拟模块改善了至少与存储器控制器最接近的存储器模块的信号完整性。

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