公开(公告)号：US20130320294A1

公开(公告)日：2013-12-05

申请号：US13996506

申请日：2011-12-23

申请人： Annalisa Cappellani ,  Peter G. Tolchinsky ,  Kelin J. Kuhn ,  Glenn A. Glass ,  Van H. Le

发明人： Annalisa Cappellani ,  Peter G. Tolchinsky ,  Kelin J. Kuhn ,  Glenn A. Glass ,  Van H. Le

IPC分类号： H01L29/04

CPC分类号： H01L29/045 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78687 ,  H01L29/78696

摘要： Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate.

摘要翻译： 描述具有不同材料取向或组成的纳米线或半导体主体的共基板半导体器件以及形成这种共基板器件的方法。 例如，半导体结构包括具有设置在结晶衬底之上的第一纳米线或半导体本体的第一半导体器件。 第一纳米线或半导体主体由具有第一全局晶体取向的半导体材料组成。 半导体结构还包括具有设置在晶体衬底上方的第二纳米线或半导体本体的第二半导体器件。 第二纳米线或半导体本体由具有与第一全局取向不同的第二全局晶体取向的半导体材料组成。 通过设置在第二纳米线或半导体本体与晶体衬底之间的隔离基座将第二纳米线或半导体本体与晶体衬底隔离。

公开(公告)号：US20130161756A1

公开(公告)日：2013-06-27

申请号：US13560531

申请日：2012-07-27

申请人： Glenn A. Glass ,  Kelin J. Kuhn ,  Seiyon Kim ,  Anand S. Murthy ,  Daniel B. Aubertine

发明人： Glenn A. Glass ,  Kelin J. Kuhn ,  Seiyon Kim ,  Anand S. Murthy ,  Daniel B. Aubertine

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L29/0676 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/7855 ,  H01L29/78696

摘要： Techniques are disclosed for customization of nanowire transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom material stacks of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type layer stack, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type layer stack. The p-type layer stack can be completely independent of the process for the n-type layer stack, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

公开(公告)号：US20170133277A1

公开(公告)日：2017-05-11

申请号：US15411095

申请日：2017-01-20

申请人： Seiyon KIM ,  Kelin J. KUHN ,  Tahir GHANI ,  Anand S. MURTHY ,  Annalisa CAPPELLANI ,  Stephen M. CEA ,  Rafael RIOS ,  Glenn A. GLASS

发明人： Seiyon KIM ,  Kelin J. KUHN ,  Tahir GHANI ,  Anand S. MURTHY ,  Annalisa CAPPELLANI ,  Stephen M. CEA ,  Rafael RIOS ,  Glenn A. GLASS

IPC分类号： H01L21/8238 ,  H01L29/423 ,  H01L27/12 ,  H01L29/06 ,  H01L27/092 ,  H01L21/84

CPC分类号： H01L21/823821 ,  B82Y10/00 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823828 ,  H01L21/84 ,  H01L21/845 ,  H01L27/092 ,  H01L27/0924 ,  H01L27/12 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7853

摘要： Complimentary metal-oxide-semiconductor nanowire structures are described. For example, a semiconductor structure includes a first semiconductor device. The first semiconductor device includes a first nanowire disposed above a substrate. The first nanowire has a mid-point a first distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. A first gate electrode stack completely surrounds the discrete channel region of the first nanowire. The semiconductor structure also includes a second semiconductor device. The second semiconductor device includes a second nanowire disposed above the substrate. The second nanowire has a mid-point a second distance above the substrate and includes a discrete channel region and source and drain regions on either side of the discrete channel region. The first distance is different from the second distance. A second gate electrode stack completely surrounds the discrete channel region of the second nanowire.

公开(公告)号：US09564522B2

公开(公告)日：2017-02-07

申请号：US14803919

申请日：2015-07-20

申请人： Stephen M. Cea ,  Annalisa Cappellani ,  Martin D. Giles ,  Rafael Rios ,  Seiyon Kim ,  Kelin J. Kuhn

发明人： Stephen M. Cea ,  Annalisa Cappellani ,  Martin D. Giles ,  Rafael Rios ,  Seiyon Kim ,  Kelin J. Kuhn

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66 ,  H01L21/268 ,  H01L29/786 ,  H01L29/78 ,  B82Y40/00

CPC分类号： H01L29/78618 ,  B82Y40/00 ,  H01L21/268 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/66787 ,  H01L29/66977 ,  H01L29/7839 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/78651 ,  H01L29/78684 ,  H01L29/78696

摘要： Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

摘要翻译： 描述了具有非离散源极和漏极区域的纳米线结构。 例如，半导体器件包括设置在衬底上方的多个垂直堆叠的纳米线。 每个纳米线包括设置在纳米线中的离散通道区域。 栅电极堆叠围绕多个垂直堆叠的纳米线。 一对非离散源极和漏极区域设置在多个垂直堆叠的纳米线的离散沟道区域的两侧并邻接。

公开(公告)号：US20160336219A1

公开(公告)日：2016-11-17

申请号：US15219138

申请日：2016-07-25

申请人： Annalisa Cappellani ,  Kelin J. Kuhn ,  Rafael Rios ,  Harry Gomez

发明人： Annalisa Cappellani ,  Kelin J. Kuhn ,  Rafael Rios ,  Harry Gomez

IPC分类号： H01L21/762 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L21/76237 ,  H01L21/76232 ,  H01L27/088 ,  H01L27/1207 ,  H01L29/0638 ,  H01L29/0653 ,  H01L29/7851

摘要： Isolated and bulk semiconductor devices formed on a same bulk substrate and methods to form such devices are described. For example, a semiconductor structure includes a first semiconductor device having a first semiconductor body disposed on a bulk substrate. The first semiconductor body has an uppermost surface with a first horizontal plane. The semiconductor structure also includes a second semiconductor device having a second semiconductor body disposed on an isolation pedestal. The isolation pedestal is disposed on the bulk substrate. The second semiconductor body has an uppermost surface with a second horizontal plane. The first and second horizontal planes are co-planar.

摘要翻译： 描述了形成在相同体积基板上的隔离和体半导体器件以及形成这种器件的方法。 例如，半导体结构包括具有设置在体基板上的第一半导体本体的第一半导体器件。 第一半导体本体具有带有第一水平面的最上表面。 半导体结构还包括具有设置在隔离基座上的第二半导体本体的第二半导体器件。 隔离基座设置在主体基板上。 第二半导体本体具有带有第二水平面的最上表面。 第一和第二水平面是共面的。

公开(公告)号：US09484447B2

公开(公告)日：2016-11-01

申请号：US13539195

申请日：2012-06-29

申请人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Mark Armstrong ,  Rafael Rios ,  Abhijit Jayant Pethe ,  Willy Rachmady

发明人： Seiyon Kim ,  Kelin J. Kuhn ,  Tahir Ghani ,  Anand S. Murthy ,  Mark Armstrong ,  Rafael Rios ,  Abhijit Jayant Pethe ,  Willy Rachmady

IPC分类号： H01L29/78 ,  H01L21/336 ,  B82Y40/00 ,  B82Y99/00 ,  H01L29/06 ,  H01L29/786

CPC分类号： H01L29/0673 ,  B82Y40/00 ,  H01L21/30604 ,  H01L21/3105 ,  H01L21/31155 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/78 ,  H01L29/78696

摘要： A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

摘要翻译： 公开了一种具有多个内部间隔物的纳米线器件和用于形成所述内部间隔物的方法。 在一个实施例中，半导体器件包括设置在衬底上方的纳米线堆叠，纳米线堆叠具有多个垂直堆叠的纳米线，围绕多个纳米线中的每一个缠绕的栅极结构，限定器件的沟道区，栅极 结构，其具有栅极侧壁，在沟道区域的相对侧上的一对源极/漏极区域; 以及位于纳米线堆叠内部的两个相邻纳米线之间的栅极侧壁的一部分上的内部间隔物。 在一个实施例中，内部间隔物通过在与沟道区相邻蚀刻的凹坑中沉积间隔物形成。 在一个实施例中，通过沟道区蚀刻凹坑。 在另一个实施例中，通过源/漏区蚀刻凹坑。

公开(公告)号：US09087863B2

公开(公告)日：2015-07-21

申请号：US13995930

申请日：2011-12-23

申请人： Stephen M. Cea ,  Annalisa Cappellani ,  Martin D. Giles ,  Rafael Rios ,  Seiyon Kim ,  Kelin J. Kuhn

发明人： Stephen M. Cea ,  Annalisa Cappellani ,  Martin D. Giles ,  Rafael Rios ,  Seiyon Kim ,  Kelin J. Kuhn

IPC分类号： H01L29/06 ,  H01L21/336 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786 ,  H01L21/268 ,  H01L29/78 ,  B82Y40/00

CPC分类号： H01L29/78618 ,  B82Y40/00 ,  H01L21/268 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/66742 ,  H01L29/66787 ,  H01L29/66977 ,  H01L29/7839 ,  H01L29/7845 ,  H01L29/7848 ,  H01L29/78651 ,  H01L29/78684 ,  H01L29/78696

摘要： Nanowire structures having non-discrete source and drain regions are described. For example, a semiconductor device includes a plurality of vertically stacked nanowires disposed above a substrate. Each of the nanowires includes a discrete channel region disposed in the nanowire. A gate electrode stack surrounds the plurality of vertically stacked nanowires. A pair of non-discrete source and drain regions is disposed on either side of, and adjoining, the discrete channel regions of the plurality of vertically stacked nanowires.

摘要翻译： 描述了具有非离散源极和漏极区域的纳米线结构。 例如，半导体器件包括设置在衬底上方的多个垂直堆叠的纳米线。 每个纳米线包括设置在纳米线中的离散通道区域。 栅电极堆叠围绕多个垂直堆叠的纳米线。 一对非离散源极和漏极区域设置在多个垂直堆叠的纳米线的离散沟道区域的两侧并邻接。

公开(公告)号：US20150179786A1

公开(公告)日：2015-06-25

申请号：US14138254

申请日：2013-12-23

申请人： Seiyon Kim ,  Kelin J. Kuhn

发明人： Seiyon Kim ,  Kelin J. Kuhn

IPC分类号： H01L29/78 ,  H01L29/423 ,  H01L29/41 ,  H01L29/66 ,  H01L29/51

CPC分类号： H01L29/785 ,  H01L21/565 ,  H01L29/66795

摘要： An embodiment concerns selective etching of a structure (e.g., a fin) to form a void with the shape of the original structure. This void then functions as a mold. Flowable dielectric material fills the void to form the same shape as the original structure/mold. Post-processing then occurs (e.g., oxidation build up and annealing) to harden the dielectric in the void. The resulting product is a molded dielectric nanostructure that has the same shape as the original structure but consists of a different material (e.g., dielectric instead of silicon). Other embodiments are described herein.

摘要翻译： 实施例涉及对结构（例如，翅片）的选择性蚀刻以形成具有原始结构形状的空隙。 该空隙然后用作模具。 可流动介电材料填充空隙以形成与原始结构/模具相同的形状。 然后发生后处理（例如，氧化堆积和退火）以使空隙中的电介质硬化。 所得到的产品是模制的电介质纳米结构，其具有与原始结构相同的形状，但由不同的材料（例如电介质代替硅）构成。 本文描述了其它实施例。

公开(公告)号：US20150041847A1

公开(公告)日：2015-02-12

申请号：US14521200

申请日：2014-10-22

申请人： Roza Kotlyar ,  Stephen M. Cea ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Rafael Rios ,  Anurag Chaudhry ,  Thomas D. Linton, JR. ,  Ian A. Young ,  Kelin J. Kuhn

发明人： Roza Kotlyar ,  Stephen M. Cea ,  Gilbert Dewey ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Rafael Rios ,  Anurag Chaudhry ,  Thomas D. Linton, JR. ,  Ian A. Young ,  Kelin J. Kuhn

IPC分类号： H01L29/78 ,  H01L29/267 ,  H01L29/06 ,  H01L29/24 ,  H01L29/16

CPC分类号： H01L29/66977 ,  H01L27/092 ,  H01L29/045 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/161 ,  H01L29/165 ,  H01L29/20 ,  H01L29/24 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/7391 ,  H01L29/7842 ,  H01L29/785 ,  H01L29/78603 ,  H01L29/78642 ,  H01L29/78684 ,  H01L29/78696

摘要： Tunneling field effect transistors (TFETs) for CMOS architectures and approaches to fabricating N-type and P-type TFETs are described. For example, a tunneling field effect transistor (TFET) includes a homojunction active region disposed above a substrate. The homojunction active region includes a relaxed Ge or GeSn body having an undoped channel region therein. The homojunction active region also includes doped source and drain regions disposed in the relaxed Ge or GeSn body, on either side of the channel region. The TFET also includes a gate stack disposed on the channel region, between the source and drain regions. The gate stack includes a gate dielectric portion and gate electrode portion.

摘要翻译： 描述了用于CMOS架构的隧道场效应晶体管（TFET）和制造N型和P型TFET的方法。 例如，隧道场效应晶体管（TFET）包括设置在衬底上方的均质有源区。 同质结有源区包括其中具有未掺杂沟道区的松弛Ge或GeSn体。 同质结有源区还包括设置在放大的Ge或GeSn体中，在沟道区两侧的掺杂源极和漏极区。 TFET还包括设置在沟道区域之间的源极和漏极区域之间的栅极堆叠。 栅极堆叠包括栅极电介质部分和栅极电极部分。

公开(公告)号：US20140326952A1

公开(公告)日：2014-11-06

申请号：US14274592

申请日：2014-05-09

申请人： Kelin J. KUHN ,  Seiyon KIM ,  Rafael RIOS ,  Stephen M. Cea ,  Martin D. GILES ,  Annalisa CAPPELLANI ,  Titash RAKSHIT ,  Peter CHANG ,  Willy RACHMADY

发明人： Kelin J. KUHN ,  Seiyon KIM ,  Rafael RIOS ,  Stephen M. Cea ,  Martin D. GILES ,  Annalisa CAPPELLANI ,  Titash RAKSHIT ,  Peter CHANG ,  Willy RACHMADY

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L29/78

CPC分类号： H01L29/0673 ,  B82Y10/00 ,  H01L21/76224 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/0676 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/165 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/785 ,  H01L29/78618 ,  H01L29/78654 ,  H01L29/78684 ,  H01L29/78696

摘要： Methods of forming microelectronic structures are described. Embodiments of those methods include forming a nanowire device comprising a substrate comprising source/drain structures adjacent to spacers, and nanowire channel structures disposed between the spacers, wherein the nanowire channel structures are vertically stacked above each other.

摘要翻译： 描述形成微电子结构的方法。 这些方法的实施例包括形成纳米线装置，其包括基板，该基板包括与间隔物相邻的源极/漏极结构，以及设置在间隔物之间​​的纳米线通道结构，其中纳米线通道结构在彼此之上垂直堆叠。