公开(公告)号：US09559160B2

公开(公告)日：2017-01-31

申请号：US13996506

申请日：2011-12-23

申请人： Annalisa Cappellani ,  Peter G. Tolchinsky ,  Kelin J. Kuhn ,  Glenn A. Glass ,  Van H. Le

发明人： Annalisa Cappellani ,  Peter G. Tolchinsky ,  Kelin J. Kuhn ,  Glenn A. Glass ,  Van H. Le

IPC分类号： H01L29/04 ,  H01L29/66 ,  H01L29/775 ,  H01L27/12 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/06 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L29/045 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78687 ,  H01L29/78696

摘要： Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate.

摘要翻译： 描述具有不同材料取向或组成的纳米线或半导体主体的共基板半导体器件以及形成这种共基板器件的方法。 例如，半导体结构包括具有设置在结晶衬底之上的第一纳米线或半导体本体的第一半导体器件。 第一纳米线或半导体主体由具有第一全局晶体取向的半导体材料组成。 半导体结构还包括具有设置在晶体衬底上方的第二纳米线或半导体本体的第二半导体器件。 第二纳米线或半导体本体由具有与第一全局取向不同的第二全局晶体取向的半导体材料组成。 通过设置在第二纳米线或半导体本体与晶体衬底之间的隔离基座，将第二纳米线或半导体本体与晶体衬底隔离。

公开(公告)号：US20130320294A1

公开(公告)日：2013-12-05

申请号：US13996506

申请日：2011-12-23

申请人： Annalisa Cappellani ,  Peter G. Tolchinsky ,  Kelin J. Kuhn ,  Glenn A. Glass ,  Van H. Le

发明人： Annalisa Cappellani ,  Peter G. Tolchinsky ,  Kelin J. Kuhn ,  Glenn A. Glass ,  Van H. Le

IPC分类号： H01L29/04

CPC分类号： H01L29/045 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/823821 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78687 ,  H01L29/78696

摘要： Common-substrate semiconductor devices having nanowires or semiconductor bodies with differing material orientation or composition and methods to form such common-substrate devices are described. For example, a semiconductor structure includes a first semiconductor device having a first nanowire or semiconductor body disposed above a crystalline substrate. The first nanowire or semiconductor body is composed of a semiconductor material having a first global crystal orientation. The semiconductor structure also includes a second semiconductor device having a second nanowire or semiconductor body disposed above the crystalline substrate. The second nanowire or semiconductor body is composed of a semiconductor material having a second global crystal orientation different from the first global orientation. The second nanowire or semiconductor body is isolated from the crystalline substrate by an isolation pedestal disposed between the second nanowire or semiconductor body and the crystalline substrate.

摘要翻译： 描述具有不同材料取向或组成的纳米线或半导体主体的共基板半导体器件以及形成这种共基板器件的方法。 例如，半导体结构包括具有设置在结晶衬底之上的第一纳米线或半导体本体的第一半导体器件。 第一纳米线或半导体主体由具有第一全局晶体取向的半导体材料组成。 半导体结构还包括具有设置在晶体衬底上方的第二纳米线或半导体本体的第二半导体器件。 第二纳米线或半导体本体由具有与第一全局取向不同的第二全局晶体取向的半导体材料组成。 通过设置在第二纳米线或半导体本体与晶体衬底之间的隔离基座将第二纳米线或半导体本体与晶体衬底隔离。

公开(公告)号：US09711591B2

公开(公告)日：2017-07-18

申请号：US13997607

申请日：2011-12-28

申请人： Niloy Mukherjee ,  Matthew V. Metz ,  James M. Powers ,  Van H. Le ,  Benjamin Chu-Kung ,  Mark R. Lemay ,  Marko Radosavljevic ,  Niti Goel ,  Loren Chow ,  Peter G. Tolchinsky ,  Jack T. Kavalieros ,  Robert S. Chau

发明人： Niloy Mukherjee ,  Matthew V. Metz ,  James M. Powers ,  Van H. Le ,  Benjamin Chu-Kung ,  Mark R. Lemay ,  Marko Radosavljevic ,  Niti Goel ,  Loren Chow ,  Peter G. Tolchinsky ,  Jack T. Kavalieros ,  Robert S. Chau

IPC分类号： H01L21/02 ,  H01L29/06

CPC分类号： H01L29/06 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02455 ,  H01L21/02494 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02587 ,  H01L21/0259 ,  H01L21/02617 ,  H01L21/02636 ,  H01L21/02658 ,  H01L21/02664

摘要： Methods of forming hetero-layers with reduced surface roughness and bulk defect density on non-native surfaces and the devices formed thereby are described. In one embodiment, the method includes providing a substrate having a top surface with a lattice constant and depositing a first layer on the top surface of the substrate. The first layer has a top surface with a lattice constant that is different from the first lattice constant of the top surface of the substrate. The first layer is annealed and polished to form a polished surface. A second layer is then deposited above the polished surface.

公开(公告)号：US08143646B2

公开(公告)日：2012-03-27

申请号：US11498901

申请日：2006-08-02

申请人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Loren A. Chow ,  Peter G. Tolchinsky ,  Joel M. Fastenau ,  Dmitri Loubychev ,  Amy W. K. Liu

发明人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Loren A. Chow ,  Peter G. Tolchinsky ,  Joel M. Fastenau ,  Dmitri Loubychev ,  Amy W. K. Liu

IPC分类号： H01L21/02

CPC分类号： H01L29/7785 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02466 ,  H01L21/02549 ,  H01L21/02617 ,  H01L29/66462

摘要： A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108 cm−2 to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.

摘要翻译： 描述了在硅衬底上形成III-V器件层的层叠故障和双阻挡屏障及其制造方法。 本发明的实施方案能够在硅衬底上形成缺陷密度低于1×10 8 cm -2的III-V InSb器件层。 在本发明的实施例中，缓冲层位于III-V器件层和硅衬底之间以滑动位错。 在本发明的一个实施例中，基于晶格常数，带隙和熔点选择GaSb缓冲层，以防止许多晶格缺陷从缓冲器传播到III-V器件层中。 在具体实施例中，III-V InSb器件层直接形成在GaSb缓冲器上。

公开(公告)号：US20100327261A1

公开(公告)日：2010-12-30

申请号：US12876922

申请日：2010-09-07

申请人： Mantu K. Hudait ,  Suman Datta ,  Jack T. Kavalieros ,  Peter G. Tolchinsky

发明人： Mantu K. Hudait ,  Suman Datta ,  Jack T. Kavalieros ,  Peter G. Tolchinsky

IPC分类号： H01L29/775 ,  H01L29/20

CPC分类号： H01L29/7782 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/02573 ,  H01L21/0262 ,  H01L29/267 ,  H01L29/66431

摘要： The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

摘要翻译： 本公开提供了一种在硅（“Si”）衬底上实现高空穴迁移率p沟道锗（“Ge”）晶体管结构的装置和方法。 一个示例性装置可以包括包括GaAs成核层，第一GaAs缓冲层和第二GaAs缓冲层的缓冲层。 该示例性装置还可以包括第二GaAs缓冲层上的底部阻挡层，并具有大于1.1eV的带隙，底部势垒上的Ge活性通道层，并且相对于底部势垒的价带偏移大于0.3 eV和Ge活性通道层上的AlAs顶部势垒，其中AlAs顶部势垒具有大于1.1eV的带隙。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US07378331B2

公开(公告)日：2008-05-27

申请号：US11025131

申请日：2004-12-29

申请人： Mohamad Shaheen ,  Peter G. Tolchinsky ,  Irwin Yablok ,  Scott R. List

发明人： Mohamad Shaheen ,  Peter G. Tolchinsky ,  Irwin Yablok ,  Scott R. List

IPC分类号： H01L21/30 ,  H01L21/46

CPC分类号： H01L24/81 ,  H01L21/6835 ,  H01L21/76259 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/81001 ,  H01L2224/81801 ,  H01L2924/01033 ,  H01L2924/14

摘要： A method and article to provide a three-dimensional (3-D) IC wafer process flow. In some embodiments, the method and article include bonding a device layer of a multilayer wafer to a device layer of another multilayer wafer to form a bonded pair of device layers, each of the multilayer wafers including a layer of silicon on a layer of porous silicon (SiOPSi) on a silicon substrate where the device layer is formed in the silicon layer, separating the bonded pair of device layers from one of the silicon substrates by splitting one of the porous silicon layers, and separating the bonded pair of device layers from the remaining silicon substrate by splitting the other one of the porous silicon layers to provide a vertically stacked wafer.

摘要翻译： 一种提供三维（3-D）IC晶片工艺流程的方法和制品。 在一些实施例中，所述方法和制品包括将多层晶片的器件层接合到另一多层晶片的器件层以形成键合的器件层对，所述多层晶片中的每一个在多孔硅层上包括硅层 （SiOPSi），其中所述器件层形成在所述硅层中，通过分离所述多孔硅层之一将所述一对器件层与所述硅衬底中的一个分离，并且将所述一对器件层与所述多个硅层分离 通过分离另一个多孔硅层来提供剩余的硅衬底以提供垂直堆叠的晶片。

公开(公告)号：US08217383B2

公开(公告)日：2012-07-10

申请号：US12876922

申请日：2010-09-07

申请人： Mantu K. Hudait ,  Suman Datta ,  Jack T. Kavalieros ,  Peter G. Tolchinsky

发明人： Mantu K. Hudait ,  Suman Datta ,  Jack T. Kavalieros ,  Peter G. Tolchinsky

IPC分类号： H01L29/775 ,  H01L29/20

CPC分类号： H01L29/7782 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02546 ,  H01L21/02573 ,  H01L21/0262 ,  H01L29/267 ,  H01L29/66431

摘要： The present disclosure provides an apparatus and method for implementing a high hole mobility p-channel Germanium (“Ge”) transistor structure on a Silicon (“Si”) substrate. One exemplary apparatus may include a buffer layer including a GaAs nucleation layer, a first GaAs buffer layer, and a second GaAs buffer layer. The exemplary apparatus may further include a bottom barrier on the second GaAs buffer layer and having a band gap greater than 1.1 eV, a Ge active channel layer on the bottom barrier and having a valence band offset relative to the bottom barrier that is greater than 0.3 eV, and an AlAs top barrier on the Ge active channel layer wherein the AlAs top barrier has a band gap greater than 1.1 eV. Of course, many alternatives, variations and modifications are possible without departing from this embodiment.

摘要翻译： 本公开提供了一种在硅（“Si”）衬底上实现高空穴迁移率p沟道锗（“Ge”）晶体管结构的装置和方法。 一个示例性装置可以包括包括GaAs成核层，第一GaAs缓冲层和第二GaAs缓冲层的缓冲层。 该示例性装置还可以包括第二GaAs缓冲层上的底部阻挡层，并具有大于1.1eV的带隙，底部势垒上的Ge活性通道层，并且相对于底部势垒的价带偏移大于0.3 eV和Ge活性通道层上的AlAs顶部势垒，其中AlAs顶部势垒具有大于1.1eV的带隙。 当然，在不脱离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US20120142166A1

公开(公告)日：2012-06-07

申请号：US13366143

申请日：2012-02-03

申请人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Loren A. Chow ,  Peter G. Tolchinsky ,  Joel M. Fastenau ,  Dmitri Loubychev ,  Amy W.K. Liu

发明人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Loren A. Chow ,  Peter G. Tolchinsky ,  Joel M. Fastenau ,  Dmitri Loubychev ,  Amy W.K. Liu

IPC分类号： H01L21/20

CPC分类号： H01L29/7785 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02466 ,  H01L21/02549 ,  H01L21/02617 ,  H01L29/66462

摘要： A stacking fault and twin blocking barrier for forming a III-V device layer on a silicon substrate and the method of manufacture is described. Embodiments of the present invention enable III-V InSb device layers with defect densities below 1×108cm−2 to be formed on silicon substrates. In an embodiment of the present invention, a buffer layer is positioned between a III-V device layer and a silicon substrate to glide dislocations. In an embodiment of the present invention, GaSb buffer layer is selected on the basis of lattice constant, band gap, and melting point to prevent many lattice defects from propagating out of the buffer into the III-V device layer. In a specific embodiment, a III-V InSb device layer is formed directly on the GaSb buffer.

摘要翻译： 描述了在硅衬底上形成III-V器件层的层叠故障和双阻挡屏障及其制造方法。 本发明的实施方案能够在硅衬底上形成缺陷密度低于1×108cm-2的III-V InSb器件层。 在本发明的实施例中，缓冲层位于III-V器件层和硅衬底之间以滑动位错。 在本发明的一个实施例中，基于晶格常数，带隙和熔点选择GaSb缓冲层，以防止许多晶格缺陷从缓冲器传播到III-V器件层中。 在具体实施例中，III-V InSb器件层直接形成在GaSb缓冲器上。

公开(公告)号：US07851781B2

公开(公告)日：2010-12-14

申请号：US12378407

申请日：2009-02-13

申请人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Loren A. Chow ,  Peter G. Tolchinsky ,  Joel M. Fastenau ,  Dmitri Loubychev ,  Amy W. K. Liu

发明人： Mantu K. Hudait ,  Mohamad A. Shaheen ,  Loren A. Chow ,  Peter G. Tolchinsky ,  Joel M. Fastenau ,  Dmitri Loubychev ,  Amy W. K. Liu

IPC分类号： H01L31/00

CPC分类号： H01L29/7784 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02466 ,  H01L21/02502 ,  H01L21/02505 ,  H01L21/02549 ,  H01L29/045 ,  H01L29/201 ,  H01L29/205 ,  H01L29/66462

摘要： Various embodiments provide a buffer layer that is grown over a silicon substrate that provides desirable device isolation for devices formed relative to III-V material device layers, such as InSb-based devices, as well as bulk thin film grown on a silicon substrate. In addition, the buffer layer can mitigate parallel conduction issues between transistor devices and the silicon substrate. In addition, the buffer layer addresses and mitigates lattice mismatches between the film relative to which the transistor is formed and the silicon substrate.

摘要翻译： 各种实施例提供了在硅衬底上生长的缓冲层，其为相对于III-V材料器件层（例如基于InSb的器件）形成的器件以及在硅衬底上生长的体薄膜提供期望的器件隔离。 此外，缓冲层可以减轻晶体管器件和硅衬底之间的并联传导问题。 此外，缓冲层解决了薄膜相对于其形成晶体管和硅衬底之间的晶格失配。

公开(公告)号：US20090315018A1

公开(公告)日：2009-12-24

申请号：US12214737

申请日：2008-06-19

申请人： Mantu K. Hudait ,  Peter G. Tolchinsky ,  Loren A. Chow ,  Dmitri Loubychev ,  Joel M. Fastenau ,  Amy W.K. Liu

发明人： Mantu K. Hudait ,  Peter G. Tolchinsky ,  Loren A. Chow ,  Dmitri Loubychev ,  Joel M. Fastenau ,  Amy W.K. Liu

IPC分类号： H01L29/12 ,  H01L21/205

CPC分类号： H01L21/02546 ,  B82Y10/00 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02505 ,  H01L21/0251 ,  H01L29/127 ,  H01L29/205 ,  H01L29/66462

摘要： Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a GaSb nucleation layer on a substrate, forming a Ga(Al)AsSb buffer layer on the GaSb nucleation layer, forming an In0.52Al0.48As bottom barrier layer on the Ga(Al)AsSb buffer layer, and forming a graded InxAl1-xAs layer on the In0.52Al0.48As bottom barrier layer thus enabling the fabrication of low defect, device grade InGaAs based quantum well structures.

摘要翻译： 描述形成微电子器件的方法和相关结构。 这些方法可以包括在衬底上形成GaSb成核层，在GaSb成核层上形成Ga（Al）AsSb缓冲层，在Ga（Al）AsSb缓冲层上形成In0.52Al0.48As底部阻挡层，并形成 因此In0.52Al0.48As底部阻挡层上的渐变InxAl1-xAs层因此能够制造低缺陷，基于器件级InGaAs的量子阱结构。