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51.发明申请公开(公告)号：US20110104827A1
公开(公告)日：2011-05-05
申请号：US12612258
申请日：2009-11-04
申请人： Michael C. Gaidis
发明人： Michael C. Gaidis
IPC分类号： H01L43/12
CPC分类号： H01L27/222 , B82Y10/00 , H01L43/12 , Y10S438/947 , Y10S977/888
摘要： A method for fabricating a magnetoresistive random access memory (MRAM) includes forming a mask over a magnetic layer; forming a template on the mask; applying a diblock copolymer to the template; curing the diblock copolymer to form a first plurality of uniform shapes registered to the template; etching the mask to form a second plurality of uniform shapes; and etching the magnetic layer to form a third plurality of uniform shapes, the third plurality of uniform shapes comprising a plurality of magnetic tunnel junctions (MTJs). A diblock copolymer mask for fabricating a magnetoresistive random access memory (MRAM) includes a magnetic layer; a mask formed on the magnetic layer; a template formed on the mask; and a diblock copolymer mask comprising a plurality of uniform shapes formed on and registered to the template.
摘要翻译： 制造磁阻随机存取存储器（MRAM）的方法包括在磁性层上形成掩模; 在掩模上形成模板; 将二嵌段共聚物施加到模板上; 固化二嵌段共聚物以形成注册到模板的第一多个均匀形状; 蚀刻掩模以形成第二多个均匀形状; 并且蚀刻所述磁性层以形成第三多个均匀形状，所述第三多个均匀形状包括多个磁隧道结（MTJ）。 用于制造磁阻随机存取存储器（MRAM）的二嵌段共聚物掩模包括磁性层; 形成在磁性层上的掩模; 掩模上形成的模板; 和二嵌段共聚物掩模，其包含在模板上形成并登记在模板上的多个均匀形状。
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公开(公告)号：US07514271B2
公开(公告)日：2009-04-07
申请号：US11694183
申请日：2007-03-30
申请人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L. C. Hsu , Carl Radens , Keith Kwong-Hon Wong , Chih-Chao Yang
发明人： Michael C. Gaidis , Lawrence A. Clevenger , Timothy J. Dalton , John K. DeBrosse , Louis L. C. Hsu , Carl Radens , Keith Kwong-Hon Wong , Chih-Chao Yang
CPC分类号： G11C19/0841 , B82Y10/00 , G11C5/02 , G11C11/161 , G11C11/1675 , Y10T29/53165
摘要： A method of forming a magnetic domain wall memory apparatus with write/read capability includes forming a plurality of coplanar shift register structures each comprising an elongated track formed from a ferromagnetic material having a plurality of magnetic domains therein, the shift register structures further having a plurality of discontinuities therein to facilitate domain wall location: forming a magnetic read element associated with each of the shift register structures: and forming a magnetic write element associated with each of the shift register structures, the magnetic write element further comprising a write wire having a constriction therein, the constriction located at a point corresponding to the location of one of the plurality of discontinuities in the associated shift register structure.
摘要翻译： 形成具有写入/读取能力的磁畴壁存储装置的方法包括形成多个共面移位寄存器结构，每个包括由其中具有多个磁畴的铁磁材料形成的细长轨道，移位寄存器结构还具有多个 其中的不连续性以便于域壁位置：形成与每个移位寄存器结构相关联的磁读取元件;以及形成与每个移位寄存器结构相关联的磁写元件，所述磁写入元件还包括具有收缩的写入线 其中，所述收缩部位于与相关联的移位寄存器结构中的所述多个不连续之一的位置相对应的点处。
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53.发明申请METHOD AND APPARATUS FOR FABRICATING SUB-LITHOGRAPHY DATA TRACKS FOR USE IN MAGNETIC SHIFT REGISTER MEMORY DEVICES 有权用于制作用于磁移位置存储器件的次数据轨迹的方法和装置公开(公告)号：US20090046493A1
公开(公告)日：2009-02-19
申请号：US11838663
申请日：2007-08-14
申请人： SOLOMON ASSEFA , Michael C. Gaidis , Eric A. Joseph , Stuart Stephen Papworth Parkin , Christy S. Tyberg
发明人： SOLOMON ASSEFA , Michael C. Gaidis , Eric A. Joseph , Stuart Stephen Papworth Parkin , Christy S. Tyberg
CPC分类号： H01L27/222 , B82Y10/00 , G11C11/161 , G11C11/1673 , G11C11/1675 , G11C19/0808 , H01L21/76816 , H01L43/08
摘要： In one embodiment, the invention is a method and apparatus for fabricating sub-lithography data tracks for use in magnetic shift register memory devices. One embodiment of a memory device includes a first stack of dielectric material formed of a first dielectric material, a second stack of dielectric material surrounding the first stack of dielectric material and formed of at least a second dielectric material, and at least one data track for storing information, positioned between the first stack of dielectric material and the second stack of dielectric material, the data track having a high aspect ratio and a substantially rectangular cross section.
摘要翻译： 在一个实施例中，本发明是用于制造用于磁移位寄存器存储器件的子光刻数据磁道的方法和装置。 存储器件的一个实施例包括由第一电介质材料形成的介电材料的第一叠层，围绕第一电介质材料堆叠并由至少第二电介质材料形成的第二电介质材料叠层，以及至少一个用于 存储位于所述第一电介质材料堆叠和所述第二电介质材料堆之间的信息，所述数据轨道具有高纵横比和基本上矩形的横截面。
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公开(公告)号：US07381343B2
公开(公告)日：2008-06-03
申请号：US11177008
申请日：2005-07-08
IPC分类号： B44C1/22 , H01L21/302
CPC分类号： H01L43/12 , H01L21/0332 , H01L21/0337 , H01L27/11507 , H01L28/65
摘要： Techniques for magnetic device fabrication are provided. In one aspect, a method of patterning at least one, e.g., nonvolatile, material comprises the following steps. A hard mask structure is formed on at least one surface of the material to be patterned. The hard mask structure is configured to have a base, proximate to the material, and a top opposite the base. The base has one or more lateral dimensions that are greater than one or more lateral dimensions of the top of the hard mask structure, such that at least one portion of the base extends out laterally a substantial distance beyond the top. The top of the hard mask structure is at a greater vertical distance from the material being etched than the base. The material is etched.
摘要翻译： 提供了磁性器件制造技术。 一方面，图案化至少一种，例如非挥发性材料的方法包括以下步骤。 在待图案化材料的至少一个表面上形成硬掩模结构。 硬掩模结构被配置为具有靠近材料的基部和与基部相对的顶部。 基座具有大于硬掩模结构的顶部的一个或多个横向尺寸的一个或多个横向尺寸，使得基部的至少一部分横向延伸超过顶部的实质距离。 硬掩模结构的顶部距离被蚀刻的材料比基底更大的垂直距离。 材料被蚀刻。
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55.发明授权公开(公告)号：US07241668B2
公开(公告)日：2007-07-10
申请号：US10560690
申请日：2003-06-24
申请人： Michael C. Gaidis
发明人： Michael C. Gaidis
IPC分类号： H01L21/44
CPC分类号： H01L21/3212 , B82Y10/00 , H01L23/544 , H01L27/222 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A method for forming an alignment mark structure for a semiconductor device includes forming an alignment recess at a selected level of the semiconductor device substrate. A first metal layer is formed over the selected substrate level and within the alignment recess, wherein the alignment recess is formed at a depth such that the first metal layer only partially fills the alignment recess. A second metal layer is formed over the first metal layer such that the alignment recess is completely filled. The second metal layer and the first metal layer are then planarized down to the selected substrate level, thereby creating a sacrificial plug of the second layer material within the alignment recess. The sacrificial plug is removed in a manner so as not to substantially roughen the planarized surface at the selected substrate level.
摘要翻译： 用于形成半导体器件的对准标记结构的方法包括在半导体器件衬底的选定电平处形成对准凹槽。 第一金属层形成在所选择的基底层上并且在对准凹槽内，其中对准凹部形成在使得第一金属层仅部分地填充对准凹槽的深度。 在第一金属层上形成第二金属层，使得对准凹部完全填充。 然后将第二金属层和第一金属层平坦化到所选择的基底水平，从而在对准凹槽内产生第二层材料的牺牲塞。 以牺牲基板水平的平坦化表面基本粗糙化的方式除去牺牲塞。
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56.发明授权Method for fabricating magnetic field concentrators as liners around conductive wires in microelectronic devices 有权制造磁场集中器作为微电子器件中导线周围的衬垫的方法公开(公告)号：US07033881B2
公开(公告)日：2006-04-25
申请号：US10710044
申请日：2004-06-15
IPC分类号： H01L21/8242
CPC分类号： H01L43/12 , G11C11/15 , G11C11/16 , H01L27/222
摘要： In an MRAM cell, the writing current is encased in a low-reluctance material that is treated in one of several ways to render the material closest to the storage element ineffective to carry magnetic flux, thereby establishing a horseshoe-shaped cross section that focuses the flux toward the storage element.
摘要翻译： 在MRAM单元中，写入电流被封装在低磁阻材料中，其以几种方式之一进行处理，以使得最靠近存储元件的材料无效地携带磁通量，从而建立了马蹄形横截面，其将 向储存元件的通量。
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公开(公告)号：US06974770B2
公开(公告)日：2005-12-13
申请号：US10600034
申请日：2003-06-20
IPC分类号： H01L21/60 , H01L21/4763 , H01L21/311
CPC分类号： H01L21/76897 , H01L21/76834
摘要： Self-aligning vias and trenches etched between adjacent lines of metallization allows the area of the dielectric substrate allocated to the via or trench to be significantly reduced without increasing the possibility of electrical shorts to the adjacent lines of metallization.
摘要翻译： 在相邻的金属化线之间蚀刻的自对准通孔和沟槽允许分配给通孔或沟槽的电介质衬底的面积显着减小，而不增加对相邻金属化线的电短路的可能性。
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公开(公告)号：US08884387B2
公开(公告)日：2014-11-11
申请号：US13568670
申请日：2012-08-07
CPC分类号： H01L43/12 , H01L27/222 , H01L43/08
摘要： A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact.
摘要翻译： 半导体器件包括包括M2图案化区域的衬底。 在M2图案化区域上形成VA柱结构。 VA柱结构包括一个减少图案化的金属层。 VA柱结构是亚光刻接触。 在氧化物层和VA柱的金属层上形成MTJ堆叠。 MTJ叠层的尺寸和MTJ叠层的形状各向异性独立于亚光刻触点的尺寸和形状各向异性。
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公开(公告)号：US08796041B2
公开(公告)日：2014-08-05
申请号：US12549799
申请日：2009-08-28
IPC分类号： H01L21/00
CPC分类号： H01L43/12 , H01L27/222 , H01L43/08
摘要： A semiconductor device includes a substrate including an M2 patterned area. A VA pillar structure is formed over the M2 patterned area. The VA pillar structure includes a substractively patterned metal layer. The VA pillar structure is a sub-lithographic contact. An MTJ stack is formed over the oxide layer and the metal layer of the VA pillar. A size of the MTJ stack and a shape anisotropy of the MTJ stack are independent of a size and a shape anisotropy of the sub-lithographic contact.
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60.发明申请MAGNETIC RANDOM ACCESS MEMORY WITH SYNTHETIC ANTIFERROMAGNETIC STORAGE LAYERS AND NON-PINNED REFERENCE LAYERS 有权具有合成抗真菌储存层和非引导参考层的磁性随机存取存储器公开(公告)号：US20140038309A1
公开(公告)日：2014-02-06
申请号：US13566132
申请日：2012-08-03
IPC分类号： H01L43/10
CPC分类号： G11C11/161 , H01L43/08 , H01L43/12 , Y10T428/31953 , Y10T428/32 , Y10T428/325
摘要： A method for fabricating a synthetic antiferromagnetic device, includes depositing a magnesium oxide spacer layer on a reference layer having a first and second ruthenium layer, depositing a cobalt iron boron layer on the magnesium oxide spacer layer; and depositing a third ruthenium layer on the cobalt iron boron layer, the third ruthenium layer having a thickness of approximately 0-18 angstroms.
摘要翻译： 一种制造合成反铁磁装置的方法，包括在具有第一和第二钌层的参考层上沉积氧化镁间隔层，在氧化镁间隔层上沉积钴铁硼层; 以及在所述钴铁硼层上沉积第三钌层，所述第三钌层的厚度约为0-18埃。
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