Method for detecting the null current condition in a PWM driven inductor and a relative driving circuit
    51.
    发明申请
    Method for detecting the null current condition in a PWM driven inductor and a relative driving circuit 有权
    用于检测PWM驱动电感器和相对驱动电路中的零电流状态的方法

    公开(公告)号:US20040036450A1

    公开(公告)日:2004-02-26

    申请号:US10438192

    申请日:2003-05-14

    CPC classification number: H02M1/4225 Y02B70/126 Y02P80/112

    Abstract: A method for detecting a null current condition in a PWM driven inductor connected between a voltage source node and a second circuit node of a line for outputting current to a load includes generating a derivative signal by time differentiating a voltage on the second node. The method further includes monitoring an instant when the derivative signal becomes negative, and signaling verification of the null current condition each time the derivative signal becomes negative.

    Abstract translation: 用于检测连接在用于向负载输出电流的线路的电压源节点和第二电路节点之间的PWM驱动电感器中的零电流状态的方法包括通过时间微分第二节点上的电压来产生导数信号。 该方法还包括监视导数信号变为负的瞬间,以及每当导数信号变为负时,对零电流状态的信令验证。

    Motion estimation method and stabilization method for an image sequence
    52.
    发明申请
    Motion estimation method and stabilization method for an image sequence 有权
    图像序列的运动估计方法和稳定方法

    公开(公告)号:US20040027454A1

    公开(公告)日:2004-02-12

    申请号:US10462090

    申请日:2003-06-13

    CPC classification number: G06T7/215

    Abstract: A method of estimating a global motion vector representative of the motion of a first digital image with respect to a second digital image, the first and the second image forming part of a sequence of images and being made up of, respectively, a first and a second pixel matrix. The method estimates the global motion vector on the basis of the estimate of at least one motion vector of at least one region of the first image representative of the motion of the at least one region from the first image to the second image and comprising phases of: subdividing the at least one region of the first image into a plurality of pixel blocks, assigning to each block of the plurality a respective weighting coefficient calculated on the basis of a respective inhomogeneity measure, and estimating the at least one motion vector of said at least one region on the basis of the weighting coefficients assigned to each block of the at least one region.

    Abstract translation: 一种估计表示第一数字图像相对于第二数字图像的运动的全局运动矢量的方法,所述第一和第二图像形成图像序列的一部分,并且分别由第一和第二数字图像构成 第二像素矩阵。 该方法基于对从第一图像到第二图像的至少一个区域的运动的第一图像的至少一个区域的至少一个运动矢量的估计来估计全局运动矢量,并且包括 将所述第一图像的至少一个区域细分为多个像素块,向所述多个像素块中的至少一个运动矢量分配所述多个像素块中的所述至少一个运动矢量, 基于分配给所述至少一个区域的每个块的加权系数的至少一个区域。

    Method for self-calibrating a phase integration error in a modulator
    55.
    发明申请
    Method for self-calibrating a phase integration error in a modulator 有权
    用于自校正调制器中的相位积分误差的方法

    公开(公告)号:US20030149538A1

    公开(公告)日:2003-08-07

    申请号:US10329988

    申请日:2002-12-26

    CPC classification number: H03M3/38 H03M3/37 H03M3/406

    Abstract: A method of self-calibrating a modulator includes at least one integrator likely to incur a phase error may include reading a pulse response of the modulator, calculating a phase error parameter of the at least one integrator, and calibrating the phase error parameter. In addition, the calibration may provide a count of pulse response samples above suitable threshold values, as well as a change in the value of a capacitor associated with the integrator based upon the sample count.

    Abstract translation: 自校准调制器的方法包括可能引起相位误差的至少一个积分器可以包括读取调制器的脉冲响应,计算至少一个积分器的相位误差参数,以及校准相位误差参数。 此外,校准可以提供高于合适阈值的脉冲响应样本的计数,以及基于样本计数与积分器相关联的电容器的值的变化。

    Power supply circuit structure for a row decoder of a multilevel non-volatile memory device
    56.
    发明申请
    Power supply circuit structure for a row decoder of a multilevel non-volatile memory device 有权
    用于多电平非易失性存储器件的行解码器的电源电路结构

    公开(公告)号:US20030147290A1

    公开(公告)日:2003-08-07

    申请号:US10334126

    申请日:2002-12-30

    CPC classification number: G11C11/5621 G11C8/14 G11C11/56 G11C16/08 G11C16/30

    Abstract: A power supply circuit structure is useful with a row decoder for reading/writing data from/into memory cells of an integrated electrically programmable/erasable non-volatile memory device incorporating an array of multilevel memory cells. Advantageously, multiple supply voltages to the row decoder and a switching circuit for transferring the voltages over hierarchic-mode enabled conduction paths are provided.

    Abstract translation: 电源电路结构对于包含多层存储器单元阵列的集成电可编程/可擦除非易失性存储器件的/从存储单元读/写数据的行解码器是有用的。 有利地,提供了对行解码器的多个电源电压和用于将电压传送到分层模式使能的传导路径的开关电路。

    Process for sealing devices incorporating microstructures
    57.
    发明申请
    Process for sealing devices incorporating microstructures 有权
    包含微结构的密封装置的工艺

    公开(公告)号:US20030143773A1

    公开(公告)日:2003-07-31

    申请号:US10293980

    申请日:2002-11-12

    CPC classification number: B81C1/00333

    Abstract: A process for the fabrication of devices that integrate protected microstructures, comprising the following steps: forming, in a body of semiconductor material, at least one microstructure having at least one first portion and one second portion which are relatively mobile with respect to one another and are separated from one another by at least one gap region, which is accessible through a face of the body; and sealing the gap. The sealing step includes depositing on the face of the body a layer of protective material, in such a way as to close the gap region, the protective layer being such as to enable relative motion between the first portion and the second portion of the microstructure.

    Abstract translation: 一种用于制造整合受保护微结构的器件的方法,包括以下步骤:在半导体材料体中形成至少一个具有至少一个第一部分和一个第二部分的微结构,所述第一部分和第二部分相对于彼此相对移动, 通过至少一个间隙区域彼此分离,所述间隙区域可通过身体的面部接近; 并密封间隙。 所述密封步骤包括在所述主体的表面上沉积一层保护材料,以使得所述间隙区域闭合,所述保护层能够使所述微结构的第一部分和第二部分之间相对运动。

    Regulation method for the source terminal voltage in a non-volatile memory cell during a program phase and corresponding program circuit
    58.
    发明申请
    Regulation method for the source terminal voltage in a non-volatile memory cell during a program phase and corresponding program circuit 有权
    程序阶段期间非易失性存储单元中的源极端子电压的调节方法和相应的程序电路

    公开(公告)号:US20030142547A1

    公开(公告)日:2003-07-31

    申请号:US10331106

    申请日:2002-12-27

    CPC classification number: G11C16/30

    Abstract: A method and a circuit are for regulating the source terminal voltage of a non-volatile memory cell during the cell programming and/or reading phases. The method includes a phase of locally regulating the voltage value and includes comparing the source current of the cell array with a reference current. A fraction of the source current is converted to a voltage and compared with a voltage generated from a memory cell acting as a reference and being programmed to the distribution with the highest current levels. The comparison may be used for controlling a current generator to inject, into the source terminal, the current necessary to keep the predetermined voltage thereof at a constant value.

    Abstract translation: 一种方法和电路用于在单元编程和/或读取阶段期间调节非易失性存储单元的源极端子电压。 该方法包括局部调节电压值的相位,并且包括将电池阵列的源电流与参考电流进行比较。 将源电流的一部分转换成电压,并将其与作为参考的存储器单元产生的电压进行比较,并将其编程为具有最高电流电平的分布。 比较可以用于控制电流发生器向源极端子注入将其预定电压保持在恒定值所需的电流。

    Binary encoding circuit
    59.
    发明申请
    Binary encoding circuit 有权
    二进制编码电路

    公开(公告)号:US20030122693A1

    公开(公告)日:2003-07-03

    申请号:US10325707

    申请日:2002-12-20

    Inventor: Luigi Pascucci

    CPC classification number: H03M5/00

    Abstract: A binary encoding circuit is for converting at least first and second binary input signals into an output code that includes at least first and second binary output signals. The circuit may include at least one first selection circuit and at least one second selection circuit that are interconnected and comprise transistors that can be activated/deactivated, i.e. made to conduct/not conduct, according to the binary input signals. The circuit makes it possible to generate a binary code that represents the binary number of the binary input signals that are simultaneously asserted. The encoding circuit can act as a static counter, for example.

    Abstract translation: 二进制编码电路用于将至少第一和第二二进制输入信号转换成包括至少第一和第二二进制输出信号的输出代码。 电路可以包括互连的至少一个第一选择电路和至少一个第二选择电路,并且包括可以被激活/去激活的晶体管,即根据二进制输入信号导通/不导通的晶体管。 该电路使得可以生成表示同时被断言的二进制输入信号的二进制数的二进制代码。 例如,编码电路可以用作静态计数器。

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