公开(公告)号：US4954731A

公开(公告)日：1990-09-04

申请号：US344340

申请日：1989-04-26

申请人： Sang H. Dhong ,  Wei Hwang ,  Nicky C. Lu

发明人： Sang H. Dhong ,  Wei Hwang ,  Nicky C. Lu

IPC分类号： G11C11/407 ,  G11C11/408 ,  H03K5/02

CPC分类号： G11C11/4085 ,  H03K5/023

摘要： Two embodiments of a wordline boost clock circuit that can be used in high speed DRAM circuits are disclosed. The clock circuits require only one boost capacitor and discharge the wordlines faster, improving the DRAM access time. The basic feature of the clock circuit is in the floating gate structure of the nmos device which drives the load to negative during the boosting. In the first embodiment of the clock, the gate of a first device is connected to a first node through a second device. A second node, connected to a wordline, is discharged through the first and a third device when a third node is high with a fourth node low. After a sufficient discharge of the second node, the fourth node is pulled to VDD turning the second device on and a fourth device off. The first (NMOS) transistor has its gate and drain connected together and forms a diode. When a boost capacitor pulls the first node down to negative, the first device stays completely off because of its diode configuration and the second node is pulled to negative through the third device. In the second embodiment, a first device is connected between a boost capacitor and a second node. The load is discharged through a third device with a fourth device on but a first and second device off. After a sufficient discharge of the load, a fourth device is turned off but a second device is turned on, making the third device a diode. When a fifth node is pulled to ground, the second node is pulled down to negative with the first device on. In the second embodiment circuit, the load discharges through only one nmos device and consequently discharges faster than the circuit of the first embodiment.

公开(公告)号：US20110252260A1

公开(公告)日：2011-10-13

申请号：US12756570

申请日：2010-04-08

申请人： Brian K. Flachs ,  Gilles Gervais ,  Sang H. Dhong ,  Tetsuji Tamura

发明人： Brian K. Flachs ,  Gilles Gervais ,  Sang H. Dhong ,  Tetsuji Tamura

IPC分类号： G06F1/00

CPC分类号： G06F9/5094 ,  G06F1/3287 ,  G06F1/329 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24 ,  Y02D50/20

摘要： A mechanism is provided for reducing power consumed by a multi-core processor. Responsive to a number of properly functioning processor cores being more than a required number of processor cores in a multi-core processor, the power consumption measurement module determines a number of the properly functioning processor cores to disable. The power consumption measurement module initiates an equal amount of workload to be processed by each of the properly functioning processor cores. The power consumption measurement module determines power consumed by each of the properly functioning processor cores. The power consumption measurement module deactivates one or more of the properly functioning processor cores that have maximum power in order that the number of properly functioning processor cores deactivated is equal to the number of properly functioning processor cores to disable.

摘要翻译： 提供了用于减少多核处理器消耗的功率的机制。 响应于多个正常运行的处理器内核超过多核处理器中所需数量的处理器内核，功耗测量模块确定要禁用的正常运行的处理器内核的数量。 功耗测量模块启动要由每个正常运行的处理器内核处理的相同数量的工作负载。 功耗测量模块确定每个正常运行的处理器内核消耗的功耗。 功耗测量模块取消激活具有最大功率的一个或多个正常运行的处理器内核，以使已正常运行的处理器内核的数量等于要禁用的正常运行的处理器内核的数量。

公开(公告)号：US07917347B2

公开(公告)日：2011-03-29

申请号：US11927840

申请日：2007-10-30

申请人： Makoto Aikawa ,  Jonathan J. DeMent ,  Sang H. Dhong ,  Brian K. Flachs ,  Gilles Gervais ,  Iwao Takiguchi ,  Tetsuji Tamura

发明人： Makoto Aikawa ,  Jonathan J. DeMent ,  Sang H. Dhong ,  Brian K. Flachs ,  Gilles Gervais ,  Iwao Takiguchi ,  Tetsuji Tamura

IPC分类号： G06F17/50

CPC分类号： G06F17/5036 ,  G01R31/318364

摘要： Mechanisms for generating a worst case current waveform for testing of integrated circuit devices are provided. Architectural analysis of an integrated circuit device is first performed to determine an initial worst case power workload to be applied to the integrated circuit device. Thereafter, the derived worst case power workload is applied to a model and is simulated to generate a worst case current waveform that is input to an electrical model of the integrated circuit device to generate a worst case noise budget value. The worst case noise budget value is then compared to measured noise from application of the worst case power workload to a hardware implemented integrated circuit device. The worst case current waveform may be selected for future testing of integrated circuit devices or modifications to the simulation models may be performed and the process repeated based on the results of the comparison.

摘要翻译： 提供了用于产生用于集成电路器件测试的最坏情况电流波形的机构。 首先执行集成电路装置的结构分析，以确定要应用于集成电路装置的初始最坏情况功率工作负荷。 此后，将得到的最坏情况功率工作量应用于模型，并且被模拟以产生输入到集成电路器件的电气模型以产生最坏情况噪声预算值的最坏情况电流波形。 然后将最坏情况的噪声预算值与从最坏情况功率工作负载应用于硬件实现的集成电路设备的测量噪声进行比较。 可以选择最坏情况下的电流波形以用于集成电路设备的未来测试，或者可以对仿真模型进行修改，并且基于比较的结果重复该过程。

公开(公告)号：US20100102867A1

公开(公告)日：2010-04-29

申请号：US12258873

申请日：2008-10-27

申请人： Sang H. Dhong ,  Gurupada Mandal

发明人： Sang H. Dhong ,  Gurupada Mandal

IPC分类号： H03K3/289

CPC分类号： H03K3/356121

摘要： A sense amplifier based flip-flop having built-in logic functions. The flip-flop includes a first and second input circuits configured to cause complementary first and second logic values to be provided on first and second logic nodes, respectively. The flip-flop further includes a sense circuit configured to sense and capture the first and second logic values on first and second capture nodes, respectively, during an evaluation phase, and a precharge circuit configured to precharge the first and second logic node and the first and second capture nodes during a precharge phase. The flip-flop also includes a noise immunity circuit, configured to, during the evaluation phase, become active subsequent to the sense circuit capturing the first and second logic values, wherein, when activated, the noise immunity circuit prevents floating voltages on the first and second logic nodes.

摘要翻译： 具有内置逻辑功能的基于读出放大器的触发器。 触发器包括被配置为分别在第一和第二逻辑节点上提供互补的第一和第二逻辑值的第一和第二输入电路。 触发器还包括感测电路，其被配置为在评估阶段期间分别在第一和第二捕获节点上感测和捕获第一和第二逻辑值，并且预充电电路被配置为对第一和第二逻辑节点和第一 以及在预充电阶段期间的第二捕获节点。 触发器还包括噪声抗扰电路，其被配置为在评估阶段期间在感测电路捕获第一和第二逻辑值之后变得有效，其中当激活时，抗噪声电路防止浮动电压在第一和第二逻辑值 第二个逻辑节点。

公开(公告)号：US07447602B1

公开(公告)日：2008-11-04

申请号：US11758034

申请日：2007-06-05

申请人： Douglas H. Bradley ,  Jonathan J. DeMent ,  Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Yoichi Nishino

发明人： Douglas H. Bradley ,  Jonathan J. DeMent ,  Sang H. Dhong ,  Brian Flachs ,  Gilles Gervais ,  Yoichi Nishino

IPC分类号： G01R21/00 ,  G01R21/06

CPC分类号： G01R31/31721 ,  G01R31/31718

摘要： A system and method for sorting processor chips based on a thermal design point are provided. With the system and method, for each processor chip, a high power workload is run on the processor chip to determine a voltage regulator module (VRM) load line. Thereafter, a thermal design point (TDP) workload is applied to the processor chip and the voltage is varied until a performance of the processor chip falls on the VRM load line. At this point, the power input to the processor chip is measured and used to sort, or bin, the processor chip. The various workloads applied have a constant frequency. From this sorting of processor chips, high speed processors that require less voltage to achieve a desired frequency and low current processors that drain less current while running at a desired frequency may be identified.

摘要翻译： 提供了一种基于热设计点分类处理器芯片的系统和方法。 利用系统和方法，对于每个处理器芯片，在处理器芯片上运行高功率工作负载以确定电压调节器模块（VRM）负载线。 此后，将热设计点（TDP）工作量应用于处理器芯片，并且改变电压直到处理器芯片的性能落在VRM负载线上。 此时，对处理器芯片的电源输入进行测量并用于对处理器芯片进行排序或分页。 应用的各种工作负载具有恒定的频率。 从处理器芯片的这种排序中，可以识别需要较少电压以实现期望频率的低速处理器和在期望频率下运行时消耗较少电流的低电流处理器。

公开(公告)号：US06910165B2

公开(公告)日：2005-06-21

申请号：US09795899

申请日：2001-02-28

申请人： Howard H. Chen ,  Li-Kong Wang ,  Louis L. Hsu ,  Sang H. Dhong ,  Tin-chee Lo

发明人： Howard H. Chen ,  Li-Kong Wang ,  Louis L. Hsu ,  Sang H. Dhong ,  Tin-chee Lo

IPC分类号： G01R31/28 ,  H03K3/84 ,  G06F11/00

CPC分类号： H03K3/84 ,  G01R31/2841

摘要： A system and method for generating random noise for use in testing electronic devices comprises a first random pattern generator circuit for generating first sets of random bit pattern signals; one or more delay devices each receiving a trigger input signal and a random bit pattern signal set for generating in response a respective delay output signal, each delay output signal being delayed in time with respect to a respective trigger signal, a delay time being determined by the bit pattern set received; and, an oscillator circuit device associated with a respective one or more delay devices for receiving a respective delay output signal therefrom and generating a respective oscillating signal, each oscillator signal generated being used to generate artificial random noise for emulating a real noise environment in an electronic device. A second random pattern generator circuit may be provided for generating second sets of random bit pattern signals for receipt by each of the associated oscillator circuit devices in order to frequency adjust in a random manner, each of the oscillator signals.

摘要翻译： 用于产生用于测试电子设备的随机噪声的系统和方法包括：第一随机模式发生器电路，用于产生第一组随机位模式信号; 每个接收触发输入信号的一个或多个延迟装置和随机位模式信号组，用于响应于相应的延迟输出信号而产生，每个延迟输出信号相对于相应的触发信号在时间上延迟，延迟时间由 接收到位模式集; 以及与相应的一个或多个延迟装置相关联的振荡器电路装置，用于从其接收相应的延迟输出信号并产生相应的振荡信号，所产生的每个振荡器信号用于产生人造随机噪声，以仿真电子中的实际噪声环境 设备。 可以提供第二随机模式发生器电路，用于产生第二组随机位模式信号，以便由每个相关联的振荡器电路装置接收，以便随机地调整每个振荡器信号。

公开(公告)号：US5881274A

公开(公告)日：1999-03-09

申请号：US900261

申请日：1997-07-25

申请人： Hung C. Ngo ,  Joel A. Silberman ,  Sang H. Dhong

发明人： Hung C. Ngo ,  Joel A. Silberman ,  Sang H. Dhong

IPC分类号： G06F9/302 ,  G06F9/315 ,  G06F9/305

CPC分类号： G06F9/3001 ,  G06F9/30032

摘要： An apparatus for performing ADD and ROTATE as a single instruction within a processor is disclosed. In accordance with a preferred embodiment of the present invention, the apparatus comprises an adder and a rotator. The adder is utilized for adding a first number to a second number in a multiple stages to yield a carry-out and a sum output. During each of these stages, the adder produces a group generate value and a group propagate value. The rotator is utilized for rotating the group propagate value and the group generate value at each of the stages before the yielding of the carry-out and the sum output. As such, both ADD and ROTATE instructions can be completed within a single processor cycle.

摘要翻译： 公开了一种用于在处理器内执行ADD和ROTATE作为单个指令的装置。 根据本发明的优选实施例，该装置包括加法器和旋转器。 加法器用于将多个第一数字加到多个第二数目中以产生一个进位输出和一个和输出。 在每个阶段中，加法器产生组生成值和组传播值。 旋转器用于旋转组传播值，并且在进位输出和总和输出的屈服之前的组中的每个级产生组生成值。 因此，ADD和ROTATE指令都可以在单个处理器周期内完成。

公开(公告)号：US5621696A

公开(公告)日：1997-04-15

申请号：US626613

申请日：1996-01-26

申请人： Sang H. Dhong ,  Joseph J. Nocera, Jr.

发明人： Sang H. Dhong ,  Joseph J. Nocera, Jr.

IPC分类号： G11C8/00 ,  G11C8/16 ,  G11C8/02

CPC分类号： G11C8/00 ,  G11C8/16

摘要： Multiple reads are made from an array of single-read port memory cells. An array of single-read port memory cells is provided with "steering" devices located between a column of cells and the output drivers for the array. The steering devices are controlled by the read pointers such that the steering signal for a given output configuration is active only when read pointers for that output configuration are active. To complete the function, the read pointers are fed to OR gates, one per row, so that a given pointer will activate the read port of a plurality of consecutive memory cells. The read pointers represent the decoded read address and only one is active at a time.

摘要翻译： 从单个读取端口存储单元阵列进行多次读取。 提供了一个单读端口存储单元阵列，它们位于一列单元格和阵列的输出驱动器之间的“转向”器件。 转向装置由读指针控制，使得仅当该输出配置的读指针有效时，给定输出配置的转向信号才有效。 为了完成该功能，读指针被馈送到或门，每行一个，使得给定的指针将激活多个连续存储单元的读端口。 读取指针表示解码的读取地址，并且每次只有一个是活动的。

公开(公告)号：US5483179A

公开(公告)日：1996-01-09

申请号：US230265

申请日：1994-04-20

申请人： Sang H. Dhong ,  Toshiaki Kirihata ,  Matthew R. Wordeman

发明人： Sang H. Dhong ,  Toshiaki Kirihata ,  Matthew R. Wordeman

IPC分类号： H03K17/687 ,  G05F3/24 ,  H03K19/0175 ,  H01L25/00

CPC分类号： G05F3/24

摘要： A device for controlling the voltage across an NMOS pull-up transistor including a source node which may be exposed to a variable voltage. The device further includes a gate node which may be exposed to a variable voltage. A control portion regulates the voltage applied to the gate node, wherein a differential in voltage between the source node and the gate node is limited to a desired level.

摘要翻译： 用于控制跨越NMOS上拉晶体管的电压的装置，其包括可能暴露于可变电压的源节点。 该器件还包括可以暴露于可变电压的栅极节点。 控制部分调节施加到栅极节点的电压，其中源节点和栅极节点之间的电压差被限制到期望的电平。

公开(公告)号：US5418477A

公开(公告)日：1995-05-23

申请号：US52005

申请日：1993-04-22

申请人： Sang H. Dhong ,  Hyun J. Shin

发明人： Sang H. Dhong ,  Hyun J. Shin

IPC分类号： H03K19/017 ,  H03K19/0185 ,  H03K19/094

CPC分类号： H03K19/01721 ,  H03K19/018521

摘要： A pull-down circuit for a TTL compatible data output buffer uses NMOS devices. The pull-down circuit comprising two NMOS stages. Namely, a diode configuration stage where the gate and drain electrodes are shorted together during pull-down and a common-source stage. Both PMOS and NMOS devices are used for shorting the gate and drain electrodes.

摘要翻译： TTL兼容数据输出缓冲器的下拉电路使用NMOS器件。 该下拉电路包括两个NMOS级。 即，二极管配置阶段，其中栅极和漏极在下拉和共源级期间短路在一起。 PMOS和NMOS器件都用于短路栅极和漏极。