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Patent Agency Ranking
公开(公告)号：US08441860B2
公开(公告)日：2013-05-14
申请号：US13366557
申请日：2012-02-06
Applicant: Akira Goda , Taehoon Kim , Doyle Rivers , Roger Porter
Inventor： Akira Goda , Taehoon Kim , Doyle Rivers , Roger Porter
IPC: G11C16/04
CPC classification number: G11C16/10 , G11C5/145 , G11C11/5628 , G11C16/0483 , G11C16/3454 , G11C2211/5621
Abstract: Methods and memories having switching points for changing Vstep increments according to a level of a multilevel cell being programmed include programming at a smaller Vstep increment in narrow threshold voltage situations and programming at a larger Vstep increment where faster programming is desired.
Abstract translation: 具有用于根据正在编程的多电平单元的电平改变Vstep增量的切换点的方法和存储器包括在窄阈值电压情况下以较小的Vstep增量进行编程，并且在需要更快编程的较大Vstep增量下进行编程。
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公开(公告)号：US20130020720A1
公开(公告)日：2013-01-24
申请号：US13546163
申请日：2012-07-11
Applicant: Young Lyong Kim , Taehoon Kim , Jongho Lee , Chul-Yong Jang
Inventor： Young Lyong Kim , Taehoon Kim , Jongho Lee , Chul-Yong Jang
IPC: H01L25/07
CPC classification number: H01L21/76802 , H01L23/3121 , H01L23/3135 , H01L23/3185 , H01L24/24 , H01L24/82 , H01L25/0657 , H01L25/50 , H01L2224/24146 , H01L2224/24225 , H01L2224/24226 , H01L2224/24227 , H01L2224/32145 , H01L2224/32225 , H01L2224/73267 , H01L2224/76155 , H01L2224/82102 , H01L2224/92144 , H01L2225/06524 , H01L2225/06562 , H01L2225/06568 , H01L2924/01012 , H01L2924/01029 , H01L2924/12042 , H01L2924/181 , H01L2924/00
Abstract: A semiconductor package may include a substrate including a substrate connection terminal, at least one semiconductor chip stacked on the substrate and having a chip connection terminal, a first insulating layer covering at least portions of the substrate and the at least one semiconductor chip, and/or an interconnection penetrating the first insulating layer to connect the substrate connection terminal to the chip connection terminal. A semiconductor package may include stacked semiconductor chips, edge portions of the semiconductor chips constituting a stepped structure, and each of the semiconductor chips including a chip connection terminal; at least one insulating layer covering at least the edge portions of the semiconductor chips; and/or an interconnection penetrating the at least one insulating layer to connect to the chip connection terminal of each of the semiconductor chips.
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公开(公告)号：US08304876B2
公开(公告)日：2012-11-06
申请号：US12461456
申请日：2009-08-12
Applicant: Hak-Kyoon Byun , Taehoon Kim , Jongkook Kim , Sang-Uk Han , Jung-Do Lee , Seonhyang You
Inventor： Hak-Kyoon Byun , Taehoon Kim , Jongkook Kim , Sang-Uk Han , Jung-Do Lee , Seonhyang You
IPC: H01L25/11
CPC classification number: H01L25/105 , H01L23/49816 , H01L23/5387 , H01L24/48 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/1064 , H01L2924/00014 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: Provided is a semiconductor package and a method for fabricating the semiconductor package. The semiconductor package may include a first package having a first semiconductor chip mounted on a first substrate and a second package having a second semiconductor chip mounted on a second substrate, the second substrate being bent to cover a side of the first package to contact the first substrate such that the first and second packages are connected electrically.
Abstract translation: 提供半导体封装和制造半导体封装的方法。 半导体封装可以包括具有安装在第一基板上的第一半导体芯片的第一封装和安装在第二基板上的第二半导体芯片的第二封装，所述第二基板弯曲以覆盖第一封装的一侧以接触第一封装 基板，使得第一和第二封装电连接。
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公开(公告)号：US20100284219A1
公开(公告)日：2010-11-11
申请号：US12436955
申请日：2009-05-07
Applicant: Taehoon Kim , Deping He , Jeffrey Alan Kessenich
Inventor： Taehoon Kim , Deping He , Jeffrey Alan Kessenich
CPC classification number: G11C11/5628 , G11C16/3454 , G11C16/3459 , G11C2211/5621
Abstract: Methods for multiple level program verify, memory devices, and memory systems are disclosed. In one such method, a series of programming pulses are applied to a memory cell to be programmed. A program verify pulse, at an initial program verify voltage, is applied to the memory cell after each programming pulse. The initial program verify voltage is a verify voltage that has been increased by a quick charge loss voltage. The quick charge loss voltage is subtracted from the initial program verify voltage after either a programming pulse has reached a certain reference voltage or a quantity of programming pulses has reached a pulse count threshold.
Abstract translation: 公开了用于多级程序验证，存储器件和存储器系统的方法。 在一种这样的方法中，一系列编程脉冲被施加到待编程的存储器单元。 在每个编程脉冲之后，在初始程序验证电压下将程序验证脉冲施加到存储单元。 初始程序验证电压是通过快速充电损耗电压增加的验证电压。 在编程脉冲达到某个参考电压或编程脉冲数达到脉冲计数阈值之后，从初始编程验证电压中减去快速充电损耗电压。
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公开(公告)号：US20100038765A1
公开(公告)日：2010-02-18
申请号：US12461456
申请日：2009-08-12
Applicant: Hak-Kyoon Byun , Taehoon Kim , Jongkook Kim , Sang-Uk Han , Jung-Do Lee , Seonhyang You
Inventor： Hak-Kyoon Byun , Taehoon Kim , Jongkook Kim , Sang-Uk Han , Jung-Do Lee , Seonhyang You
IPC: H01L25/11
CPC classification number: H01L25/105 , H01L23/49816 , H01L23/5387 , H01L24/48 , H01L25/0657 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/0651 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/1064 , H01L2924/00014 , H01L2924/181 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
Abstract: Provided is a semiconductor package and a method for fabricating the semiconductor package. The semiconductor package may include a first package having a first semiconductor chip mounted on a first substrate and a second package having a second semiconductor chip mounted on a second substrate, the second substrate being bent to cover a side of the first package to contact the first substrate such that the first and second packages are connected electrically.
Abstract translation: 提供半导体封装和制造半导体封装的方法。 半导体封装可以包括具有安装在第一基板上的第一半导体芯片的第一封装和安装在第二基板上的第二半导体芯片的第二封装，所述第二基板弯曲以覆盖第一封装的一侧以接触第一封装 基板，使得第一和第二封装电连接。
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