公开(公告)号：US08304876B2

公开(公告)日：2012-11-06

申请号：US12461456

申请日：2009-08-12

申请人： Hak-Kyoon Byun ,  Taehoon Kim ,  Jongkook Kim ,  Sang-Uk Han ,  Jung-Do Lee ,  Seonhyang You

发明人： Hak-Kyoon Byun ,  Taehoon Kim ,  Jongkook Kim ,  Sang-Uk Han ,  Jung-Do Lee ,  Seonhyang You

IPC分类号： H01L25/11

CPC分类号： H01L25/105 ,  H01L23/49816 ,  H01L23/5387 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Provided is a semiconductor package and a method for fabricating the semiconductor package. The semiconductor package may include a first package having a first semiconductor chip mounted on a first substrate and a second package having a second semiconductor chip mounted on a second substrate, the second substrate being bent to cover a side of the first package to contact the first substrate such that the first and second packages are connected electrically.

摘要翻译： 提供半导体封装和制造半导体封装的方法。 半导体封装可以包括具有安装在第一基板上的第一半导体芯片的第一封装和安装在第二基板上的第二半导体芯片的第二封装，所述第二基板弯曲以覆盖第一封装的一侧以接触第一封装 基板，使得第一和第二封装电连接。

公开(公告)号：US20100038765A1

公开(公告)日：2010-02-18

申请号：US12461456

申请日：2009-08-12

申请人： Hak-Kyoon Byun ,  Taehoon Kim ,  Jongkook Kim ,  Sang-Uk Han ,  Jung-Do Lee ,  Seonhyang You

发明人： Hak-Kyoon Byun ,  Taehoon Kim ,  Jongkook Kim ,  Sang-Uk Han ,  Jung-Do Lee ,  Seonhyang You

IPC分类号： H01L25/11

CPC分类号： H01L25/105 ,  H01L23/49816 ,  H01L23/5387 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1064 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Provided is a semiconductor package and a method for fabricating the semiconductor package. The semiconductor package may include a first package having a first semiconductor chip mounted on a first substrate and a second package having a second semiconductor chip mounted on a second substrate, the second substrate being bent to cover a side of the first package to contact the first substrate such that the first and second packages are connected electrically.

摘要翻译： 提供半导体封装和制造半导体封装的方法。 半导体封装可以包括具有安装在第一基板上的第一半导体芯片的第一封装和安装在第二基板上的第二半导体芯片的第二封装，所述第二基板弯曲以覆盖第一封装的一侧以接触第一封装 基板，使得第一和第二封装电连接。

公开(公告)号：US08184449B2

公开(公告)日：2012-05-22

申请号：US12206355

申请日：2008-09-08

申请人： Jung-Do Lee ,  Hak-Kyoon Byun ,  Tae-Hun Kim ,  Sang-Uk Han ,  Seon-Hyang You

发明人： Jung-Do Lee ,  Hak-Kyoon Byun ,  Tae-Hun Kim ,  Sang-Uk Han ,  Seon-Hyang You

IPC分类号： H05K7/10 ,  H05K7/12

CPC分类号： H01L25/50 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/181 ,  Y10T29/49169 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electronic device includes a lower electronic part including a lower substrate, a lower chip structure disposed on the lower substrate, and a lower molding layer covering the lower chip structure and having a recessed region in an upper surface of the lower molding layer, and an upper electronic part including an upper substrate disposed on the lower electronic part, and an upper chip structure projecting from the upper substrate, wherein the recessed region of the lower molding layer receives the upper chip structure.

摘要翻译： 电子设备包括下电子部件，其包括下基板，设置在下基板上的下芯片结构，以及覆盖下芯片结构的下成型层，并且在下成型层的上表面具有凹部， 上部电子部件，其包括设置在下部电子部件上的上部基板和从上部基板突出的上部芯片结构，其中下部成型层的凹部区域接收上部芯片结构。

公开(公告)号：US20090067143A1

公开(公告)日：2009-03-12

申请号：US12206355

申请日：2008-09-08

申请人： Jung-Do Lee ,  Hak-Kyoon Byun ,  Tae-Hun Kim ,  Sang-Uk Han ,  Seon-Hyang You

发明人： Jung-Do Lee ,  Hak-Kyoon Byun ,  Tae-Hun Kim ,  Sang-Uk Han ,  Seon-Hyang You

IPC分类号： H05K1/18 ,  H05K13/00

CPC分类号： H01L25/50 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L25/03 ,  H01L25/105 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/18165 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/181 ,  Y10T29/49169 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An electronic device includes a lower electronic part including a lower substrate, a lower chip structure disposed on the lower substrate, and a lower molding layer covering the lower chip structure and having a recessed region in an upper surface of the lower molding layer, and an upper electronic part including an upper substrate disposed on the lower electronic part, and an upper chip structure projecting from the upper substrate, wherein the recessed region of the lower molding layer receives the upper chip structure.

摘要翻译： 电子设备包括下电子部件，其包括下基板，设置在下基板上的下芯片结构，以及覆盖下芯片结构的下成型层，并且在下成型层的上表面具有凹部， 上部电子部件，其包括设置在下部电子部件上的上部基板和从上部基板突出的上部芯片结构，其中下部成型层的凹部区域接收上部芯片结构。

公开(公告)号：US20070152350A1

公开(公告)日：2007-07-05

申请号：US11539133

申请日：2006-10-05

申请人： Tae-Hun Kim ,  Hak-Kyoon Byun ,  Sung-Yong Park ,  Heung-Kyu Kwon

发明人： Tae-Hun Kim ,  Hak-Kyoon Byun ,  Sung-Yong Park ,  Heung-Kyu Kwon

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H05K3/3436 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K2201/09781 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

摘要： A wiring substrate having variously sized ball pads, a semiconductor package including the wiring substrate, and a stack package using the semiconductor package, to improve board level reliability (BLR) of a semiconductor package or stack package mounted on a mother board are shown. Outer ball pads are formed to have relatively greater surface areas at the corners of the semiconductor package as compared to those at other areas and are formed to have the greatest surface area within a designable range. Additionally, occurrence of cracks may be inhibited at junctions of other solder balls by forming dummy solder pads at the outermost corners among the outer ball pads formed proximate to the corners of the wiring substrate. Stress arising during a board level reliability test is absorbed without product failure at junctions between the dummy solder pads and dummy solder balls.

摘要翻译： 示出了具有各种尺寸的球垫的布线基板，包括布线基板的半导体封装和使用半导体封装的堆叠封装，以提高安装在母板上的半导体封装或堆叠封装的电路板级可靠性（BLR）。 与其他区域相比，外球垫形成为在半导体封装的角部处具有相对较大的表面积，并且形成为具有可设计范围内的最大表面积。 此外，通过在靠近布线基板的角部形成的外球垫中的最外角处形成虚拟焊盘，可以抑制其它焊球的接合处的裂缝的发生。 在电路板级可靠性测试中产生的应力在虚拟焊盘和虚拟焊球之间的接合处被吸收而没有产品故障。

公开(公告)号：US07795743B2

公开(公告)日：2010-09-14

申请号：US11539133

申请日：2006-10-05

申请人： Tae-Hun Kim ,  Hak-Kyoon Byun ,  Sung-Yong Park ,  Heung-Kyu Kwon

发明人： Tae-Hun Kim ,  Hak-Kyoon Byun ,  Sung-Yong Park ,  Heung-Kyu Kwon

IPC分类号： H01L23/48

CPC分类号： H05K3/3436 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/562 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48471 ,  H01L2224/48479 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K2201/09781 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/4554

摘要： A wiring substrate having variously sized ball pads, a semiconductor package including the wiring substrate, and a stack package using the semiconductor package, to improve board level reliability (BLR) of a semiconductor package or stack package mounted on a mother board are shown. Outer ball pads are formed to have relatively greater surface areas at the corners of the semiconductor package as compared to those at other areas and are formed to have the greatest surface area within a designable range. Additionally, occurrence of cracks may be inhibited at junctions of other solder balls by forming dummy solder pads at the outermost corners among the outer ball pads formed proximate to the corners of the wiring substrate. Stress arising during a board level reliability test is absorbed without product failure at junctions between the dummy solder pads and dummy solder balls.

摘要翻译： 示出了具有各种尺寸的球垫的布线基板，包括布线基板的半导体封装和使用半导体封装的堆叠封装，以提高安装在母板上的半导体封装或堆叠封装的电路板级可靠性（BLR）。 与其他区域相比，外球垫形成为在半导体封装的角部处具有相对较大的表面积，并且形成为具有可设计范围内的最大表面积。 此外，通过在靠近布线基板的角部形成的外球垫中的最外角处形成虚拟焊盘，可以抑制其它焊球的接合处的裂缝的发生。 在电路板级可靠性测试中产生的应力在虚拟焊盘和虚拟焊球之间的接合处被吸收而没有产品故障。

公开(公告)号：US08531034B2

公开(公告)日：2013-09-10

申请号：US13244506

申请日：2011-09-25

申请人： Hak-Kyoon Byun ,  Dae-Young Choi ,  Mi-Yeon Kim

发明人： Hak-Kyoon Byun ,  Dae-Young Choi ,  Mi-Yeon Kim

IPC分类号： H01L23/48

CPC分类号： H01L23/49827 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17179 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform.