公开(公告)号：US11972132B2

公开(公告)日：2024-04-30

申请号：US18145810

申请日：2022-12-22

Applicant: Xilinx, Inc.

Inventor： Juan J. Noguera Serra ,  Goran H K Bilski ,  Jan Langer ,  Baris Ozgul ,  Richard L. Walke ,  Ralph D. Wittig ,  Kornelis A. Vissers ,  Tim Tuan ,  David Clarke

IPC: G06F3/06 ,  G06F13/16 ,  G06F15/173 ,  G06F15/78

CPC classification number: G06F3/0647 ,  G06F3/061 ,  G06F3/0683 ,  G06F13/1663 ,  G06F15/17331 ,  G06F15/7807

Abstract: A device includes a data processing engine array having a plurality of data processing engines organized in a grid having a plurality of rows and a plurality of columns. Each data processing engine includes a core, a memory module including a memory and a direct memory access engine. Each data processing engine includes a stream switch connected to the core, the direct memory access engine, and the stream switch of one or more adjacent data processing engines. Each memory module includes a first memory interface directly coupled to the core in the same data processing engine and one or more second memory interfaces directly coupled to the core of each of the one or more adjacent data processing engines.

公开(公告)号：US11942904B2

公开(公告)日：2024-03-26

申请号：US17402892

申请日：2021-08-16

Applicant: Xilinx, Inc.

Inventor： Hongzhi Zhao ,  Xing Zhao ,  Vincent C. Barnes ,  Xiaohan Chen ,  Hemang M. Parekh

IPC: H03F1/32 ,  H03F3/21 ,  H03G1/00

CPC classification number: H03F1/3247 ,  H03F3/21 ,  H03G1/0005 ,  H03F2201/3227

Abstract: A digital predistortion (DPD) system includes an input configured to receive an input signal. In some examples, a first signal path configured to generate a first signal based on the input signal. In some examples, an error model provider configured to generate an error model signal modeled after a gate bias error voltage associated with the DPD system. In some examples, a first combiner configured to combine the first signal and the error model signal to generate a first intermediate signal, and the DPD system generates an output signal based at least on the first intermediate signal.

公开(公告)号：US11914905B1

公开(公告)日：2024-02-27

申请号：US17377016

申请日：2021-07-15

Applicant: XILINX, INC.

Inventor： Martin Newman

IPC: G06F3/06 ,  G06F13/16

CPC classification number: G06F3/0673 ,  G06F13/1668

Abstract: Examples describe memory refresh operations for memory subsystems. One example is a method for a memory controller, the method including entering a first state upon exiting self-refresh state, wherein the first state comprises activating a first timer. The method includes entering a second state from the first state upon detecting an end of an active period and detecting that the first timer has not expired. The method includes entering a third state from the second state upon detecting expiration of the second state, wherein the third state comprises re-entering the self-refresh state.

公开(公告)号：US20240061903A1

公开(公告)日：2024-02-22

申请号：US17892852

申请日：2022-08-22

Applicant: Xilinx, Inc.

Inventor： Wenzong Yang ,  Wang Xi ,  Yadong Li ,  Junbin Wang ,  Shaoxia Fang

IPC: G06F17/16 ,  G06F7/544 ,  G06F7/552 ,  G06F7/499

CPC classification number: G06F17/16 ,  G06F7/5443 ,  G06F7/552 ,  G06F7/4991

Abstract: Circuits and methods for determining a maximum bias for computing softmax on a tensor include a processor circuit configured to transform in parallel, elements of each group of a plurality of groups of elements of a tensor X into respective power-of-two elements. The respective power-of-two element from element xt of the tensor is pt, pt=(xt*log2e), and pt has an integer part and a fraction part. A first comparison circuit (204) is configured to determine respective group-level biases for the groups. The group-level bias of groupm is dm, and dm is an integer part of a maximum of the power-of-two elements of groupm. A second comparison circuit is configured to determine a greatest one of the respective group-level biases to be a tensor-level bias, dmax.

公开(公告)号：US20240056081A1

公开(公告)日：2024-02-15

申请号：US17884342

申请日：2022-08-09

Applicant: XILINX, INC.

Inventor： Roswald FRANCIS

IPC: H03K19/0944 ,  H03K19/0185 ,  H03M1/12 ,  H03K19/0175

CPC classification number: H03K19/0944 ,  H03K19/0185 ,  H03M1/12 ,  H03K19/017545

Abstract: An electronic system includes a buffer and analog-to-digital circuitry. The buffer includes buffer circuitry that includes an input node that receives an input signal. The buffer circuitry further includes coil circuitry that is electrically connected to the input node and a first node. The coil circuitry includes a first inductor and a second inductor. Further, the buffer circuitry includes a resistor that is electrically connected to the first node and a second node. A capacitor of the buffer circuitry is electrically connected to the second node and a third node. The third node is disposed between the first inductor and the second inductor. The buffer circuitry is configured to output an output signal based on the input signal.

公开(公告)号：US11901338B2

公开(公告)日：2024-02-13

申请号：US17515354

申请日：2021-10-29

Applicant: XILINX, INC.

Inventor： Myongseob Kim ,  Henley Liu ,  Cheang Whang Chang

IPC: G01R31/28 ,  H01L21/66 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L22/32 ,  H01L24/08 ,  H01L2224/08145 ,  H01L2225/06596

Abstract: An integrated circuit (IC) device is disclosed which includes at least a first hybrid bond interface layer disposed between adjacent wafers of a wafer stack. Routing within the hybrid bond interface layer allows test pads exposed on a top wafer of the wafer stack to electrically couple test keys within the wafer stack. By utilizing the routing within the hybrid bond interface layer to index electrical connections between adjacent wafers, IC dies stacked on the wafers may be fabricated with less mask sets as compared to conventional designs.

公开(公告)号：US20240047364A1

公开(公告)日：2024-02-08

申请号：US17879670

申请日：2022-08-02

Applicant: XILINX, INC.

Inventor： Zachary BLAIR

IPC: H01L23/538 ,  H01L25/065 ,  G06F12/1027 ,  G06F15/78

CPC classification number: H01L23/5386 ,  H01L25/0657 ,  H01L23/5382 ,  G06F12/1027 ,  G06F15/7825 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541

Abstract: Embodiments herein describe a 3D stack of dies (e.g., an active-on-active (AoA) stack) with a connectivity die that enables the decoupling of processing regions in coupled dies from each other and from the physical location of I/O blocks on an I/O die. For example, the first die may have a plurality of hardware processing blocks that are arranged in a regular manner (e.g., an array with rows and columns). The connectivity die can include interconnects that couple these hardware processing blocks to I/O blocks in a second die. These I/O blocks may be arranged in an irregular manner. The interconnects in the connectivity die can provide fair access so that processing blocks on a first side of the first die can access an I/O block on the opposite side of the second die without using resources for neighboring processing blocks.

公开(公告)号：US20240046015A1

公开(公告)日：2024-02-08

申请号：US17818341

申请日：2022-08-08

Applicant: Xilinx, Inc.

Inventor： Krishnam Tibrewala

IPC: G06F30/3308 ,  G06F30/3323

CPC classification number: G06F30/3308 ,  G06F30/3323

Abstract: Providing first-in-first-out (FIFO) memory guidance for a multi-processor computing architecture includes compiling a design for a data processing array to generate a compiled design. The compiled design is mapped and routed to the data processing array. The compiled design is simulated using a modified device model of the data processing array. The modified device model uses infinite FIFO models. FIFO memory usage data is generated by tracking amounts of data stored in the infinite FIFO memory models during runtime of the simulation of the compiled design. FIFO memory requirements for one or more nets of the design are determined from the FIFO memory usage data and the compiled design.

公开(公告)号：US20240045750A1

公开(公告)日：2024-02-08

申请号：US17883379

申请日：2022-08-08

Applicant: XILINX, INC.

Inventor： Ahmad R. ANSARI ,  David P. SCHULTZ ,  Felix BURTON ,  Jeffrey CUPPETT

IPC: G06F11/07 ,  G06F9/30

CPC classification number: G06F11/0763 ,  G06F11/0772 ,  G06F9/30101

Abstract: Embodiments herein describe integrity check techniques that are efficient and flexible by using local registers in a segment to store check values which can be used to detect errors in the local configuration data in the same segment. In addition to containing local registers storing the check values, each segment can include a mask register indicated which of the configuration registers should be checked and which can be ignored. Further, the segments can include a next segment register indicating the next segment the check engine should evaluate for errors.

公开(公告)号：US20240045692A1

公开(公告)日：2024-02-08

申请号：US17818309

申请日：2022-08-08

Applicant: Xilinx, Inc.

Inventor： Xiao Teng ,  Tejus Siddagangaiah ,  Bryan Lozano ,  Ehsan Ghasemi ,  Rajeev Patwari ,  Elliott Delaye ,  Jorn Tuyls ,  Aaron Ng ,  Sanket Pandit ,  Pramod Peethambaran ,  Satyaprakash Pareek

IPC: G06F9/38 ,  G06F9/46 ,  G06F9/30

CPC classification number: G06F9/3814 ,  G06F9/467 ,  G06F9/3004

Abstract: Controlling a data processing (DP) array includes creating a replica of a register address space of the DP array based on the design and the DP array. A sequence of instructions, including write instructions and read instructions, is received. The write instructions correspond to buffer descriptors specifying runtime data movements for a design for a DP array. The write instructions are converted into transaction instructions and the read instructions are converted into wait instructions based on the replica of the register address space. The transaction instructions and the wait instructions are included in an instruction buffer. The instruction buffer is provided to a microcontroller configured to execute the transaction instructions and the wait instructions to implement the runtime data movements for the design as implemented in the DP array. In another aspect, the instruction buffer is stored in a file for subsequent execution by the microcontroller.