公开(公告)号：US07877732B2

公开(公告)日：2011-01-25

申请号：US11564417

申请日：2006-11-29

Applicant: Philip Arthur Day ,  Young Wook Lee ,  Kyle D. Robeson

Inventor： Philip Arthur Day ,  Young Wook Lee ,  Kyle D. Robeson

IPC: G06F9/44

CPC classification number: G06F11/3688 ,  G06F11/3414

Abstract: A method for efficiently stress testing a service oriented architecture based application. A business process flow is recorded between a client and a server. When an XML document is extracted from the recorded business process flow, an XML document file is created for the extracted XML document, an XML document descriptor file is created comprising XPath queries for data elements in the XML document file, a configuration file is created comprising user input parameters obtained from the recorded business process flow, and test input data file is created. The user input parameters in the configuration file are used to generate a test script to test the service oriented architecture based application, wherein data values from the test input data file are inserted into a template of the XML document file at locations specified by the XPath queries in the XML document descriptor file. The test script is then executed.

Abstract translation: 一种有效压力测试基于服务导向架构的应用程序的方法。 业务流程记录在客户端和服务器之间。 当从所记录的业务流程流中提取XML文档时，为所提取的XML文档创建XML文档文件，创建XML文档描述符文件，其包括XML文档文件中的数据元素的XPath查询，创建包括 从记录的业务处理流程获取的用户输入参数，以及测试输入数据文件被创建。 配置文件中的用户输入参数用于生成测试脚本以测试面向服务的基于架构的应用程序，其中来自测试输入数据文件的数据值被插入XML文档文件的模板中，这些位置由XPath查询指定的位置 在XML文档描述符文件中。 然后执行测试脚本。

公开(公告)号：US07759738B2

公开(公告)日：2010-07-20

申请号：US12269748

申请日：2008-11-12

Applicant: Jang-Soo Kim ,  Hong-Long Ning ,  Bong-Kyun Kim ,  Hong-Sick Park ,  Shi-Yul Kim ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Yang-Ho Bae ,  Pil-Sang Yun ,  Jong-Hyun Choung ,  Sun-Young Hong ,  Ki-Won Kim ,  Byeong-Jin Lee ,  Young-Wook Lee ,  Jong-In Kim ,  Byeong-Beom Kim ,  Nam-Seok Suh

Inventor： Jang-Soo Kim ,  Hong-Long Ning ,  Bong-Kyun Kim ,  Hong-Sick Park ,  Shi-Yul Kim ,  Chang-Oh Jeong ,  Sang-Gab Kim ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Yang-Ho Bae ,  Pil-Sang Yun ,  Jong-Hyun Choung ,  Sun-Young Hong ,  Ki-Won Kim ,  Byeong-Jin Lee ,  Young-Wook Lee ,  Jong-In Kim ,  Byeong-Beom Kim ,  Nam-Seok Suh

IPC: H01L29/04 ,  H01L29/10 ,  H01L29/15

CPC classification number: G02F1/13458 ,  G02F1/136286 ,  G02F2001/136295 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1288

Abstract: A gate line includes a first seed layer formed on a base substrate and a first metal layer formed on the first seed layer. A first insulation layer is formed on the base substrate. A second insulation layer is formed on the base substrate. Here, a line trench is formed through the second insulation layer in a direction crossing the gate line. A data line includes a second seed layer formed below the line trench and a second metal layer formed in the line trench. A pixel electrode is formed in a pixel area of the base substrate. Therefore, a trench of a predetermined depth is formed using an insulation layer and a metal layer is formed through a plating method, so that a metal line having a sufficient thickness may be formed.

Abstract translation: 栅极线包括形成在基底基板上的第一籽晶层和形成在第一籽晶层上的第一金属层。 在基底基板上形成第一绝缘层。 在基底基板上形成第二绝缘层。 这里，在与栅极线交叉的方向上通过第二绝缘层形成线沟槽。 数据线包括形成在线沟槽下方的第二晶种层和形成在线沟槽中的第二金属层。 像素电极形成在基底基板的像素区域中。 因此，使用绝缘层形成预定深度的沟槽，并且通过电镀方法形成金属层，从而可以形成具有足够厚度的金属线。

公开(公告)号：US20100140610A1

公开(公告)日：2010-06-10

申请号：US12556277

申请日：2009-09-09

Applicant: Young-Wook Lee ,  Hong-Suk Yoo ,  Jean-Ho Song ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Ki-Won Kim ,  Jang-In Kim

Inventor： Young-Wook Lee ,  Hong-Suk Yoo ,  Jean-Ho Song ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Ki-Won Kim ,  Jang-In Kim

IPC: H01L29/786 ,  H01L29/12 ,  H01L21/336

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248

Abstract: A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other.

Abstract translation: 根据本发明实施例的薄膜晶体管基板包括：绝缘基板; 形成在所述绝缘基板上的栅极线; 形成在栅极线上的第一层间绝缘层; 形成在所述第一层间绝缘层上的数据线和栅电极; 形成在数据线和栅电极上的栅极绝缘层; 形成在栅极绝缘层上并与栅电极重叠的半导体; 形成在所述半导体上的第二层间绝缘层; 形成在所述第二层间绝缘层上并将所述栅极线和所述栅电极彼此电连接的第一连接; 连接到半导体的漏电极; 连接到所述漏电极的像素电极; 以及将数据线和半导体彼此连接的第二连接。

公开(公告)号：US20090184325A1

公开(公告)日：2009-07-23

申请号：US12331044

申请日：2008-12-09

Applicant: Jeong-Min PARK ,  Doo-Hee JUNG ,  Hi-Kuk LEE ,  Young-Wook LEE

Inventor： Jeong-Min PARK ,  Doo-Hee JUNG ,  Hi-Kuk LEE ,  Young-Wook LEE

IPC: H01L33/00 ,  B44C1/22 ,  H01L21/336

CPC classification number: H01L21/2686 ,  H01L21/31058 ,  H01L27/1248 ,  H01L29/78636

Abstract: A method of planarizing a substrate. An organic layer is formed on a base substrate to cover a metal line formed on the base substrate. A portion of the organic layer is removed to form a pre-planarization layer exposing the metal layer, so that a surface of the base substrate having the metal line is planarized. The pre-planarization layer is cured to flow toward a side surface of the metal line to form a planarization layer making contact with the side surface of the metal line. Therefore, a stepped portion between the base substrate and the metal line can be minimized or substantially eliminated, thereby increasing the surface uniformity of a subsequent layer, thereby improving the reliability of the manufacturing process.

Abstract translation: 平面化基板的方法。 在基底基板上形成有机层，以覆盖形成在基底基板上的金属线。 去除有机层的一部分以形成暴露金属层的预平坦化层，使得具有金属线的基底基板的表面被平坦化。 固化预平坦化层以朝金属线的侧面流动，形成与金属线的侧面接触的平坦化层。 因此，可以将基底基板与金属线之间的阶梯部分最小化或基本上消除，从而提高后续层的表面均匀性，从而提高制造工艺的可靠性。

公开(公告)号：US20090152635A1

公开(公告)日：2009-06-18

申请号：US12331361

申请日：2008-12-09

Applicant: Yu-Gwang JEONG ,  Young-Wook Lee ,  Sang-Gab Kim ,  Woo-Geun Lee ,  Min-Seok Oh ,  Jang-Soo Kim ,  Kap-Soo Yoon ,  Shin-Il Choi ,  Hong-Kee Chin ,  Seung-Ha Choi ,  Seung-Hwan Shim ,  Sung-Hoon Yang ,  Ki-Hun Jeong

Inventor： Yu-Gwang JEONG ,  Young-Wook Lee ,  Sang-Gab Kim ,  Woo-Geun Lee ,  Min-Seok Oh ,  Jang-Soo Kim ,  Kap-Soo Yoon ,  Shin-Il Choi ,  Hong-Kee Chin ,  Seung-Ha Choi ,  Seung-Hwan Shim ,  Sung-Hoon Yang ,  Ki-Hun Jeong

IPC: H01L29/78 ,  H01L21/02

CPC classification number: H01L27/127 ,  H01L27/1214 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/66765

Abstract: Embodiments of the present invention relate to a thin film transistor and a manufacturing method of a display panel, and include forming a gate line including a gate electrode on a substrate, forming a gate insulating layer on the gate electrode, forming an intrinsic semiconductor on the gate insulating layer, forming an extrinsic semiconductor on the intrinsic semiconductor, forming a data line including a source electrode and a drain electrode on the extrinsic semiconductor, and plasma-treating a portion of the extrinsic semiconductor between the source electrode and the drain electrode to form a protection member and ohmic contacts on respective sides of the protection member. Accordingly, the process for etching the extrinsic semiconductor and forming an inorganic insulating layer for protecting the intrinsic semiconductor may be omitted such that the manufacturing process of the display panel may be simplified, manufacturing cost may be reduced, and productivity may be improved.

Abstract translation: 本发明的实施例涉及薄膜晶体管和显示面板的制造方法，包括在基板上形成包括栅电极的栅极线，在栅电极上形成栅绝缘层，在栅电极上形成本征半导体 栅极绝缘层，在本征半导体上形成非本征半导体，在外部半导体上形成包括源电极和漏电极的数据线，以及对源电极和漏极之间的非本征半导体的一部分进行等离子体处理，以形成 保护构件和保护构件的相应侧上的欧姆接触。 因此，可以省略用于蚀刻外部半导体和形成用于保护本征半导体的无机绝缘层的工艺，从而可以简化显示面板的制造工艺，可以降低制造成本，并且可以提高生产率。

公开(公告)号：US20090008646A1

公开(公告)日：2009-01-08

申请号：US12217493

申请日：2008-07-02

Applicant: Jin-Seuk Kim ,  Young-Wook Lee ,  Yui-Ku Lee

Inventor： Jin-Seuk Kim ,  Young-Wook Lee ,  Yui-Ku Lee

IPC: H01L27/02

CPC classification number: G02F1/133514 ,  G02F1/13394 ,  G02F2001/133519 ,  G02F2001/136222

Abstract: A display substrate includes a switching member, a color filter layer, an inorganic insulation layer and a pixel electrode. The switching member includes a gate line, a data line crossing the gate line, and a thin-film transistor (TFT) electrically connected to the gate line and the data line. The color filter layer is formed on the switching member. The inorganic insulation layer is formed on the color filter layer. The inorganic insulation layer has a hole formed thereon, which exposes a portion of the color filter layer in correspondence with the TFT The pixel electrode is formed on the inorganic insulation layer.

Abstract translation: 显示基板包括切换构件，滤色器层，无机绝缘层和像素电极。 开关构件包括栅极线，与栅极线交叉的数据线，以及电连接到栅极线和数据线的薄膜晶体管（TFT）。 滤色器层形成在开关元件上。 无机绝缘层形成在滤色器层上。 无机绝缘层具有形成在其上的孔，其对应于TFT曝光一部分滤色器层。在无机绝缘层上形成像素电极。

公开(公告)号：US20080252828A1

公开(公告)日：2008-10-16

申请号：US11930653

申请日：2007-10-31

Applicant: Kyoung-Ju Shin ,  Hye-Young Ryu ,  Jang-Soo Kim ,  Chong-Chul Chal ,  Jae-Hyoung Youn ,  Young-Wook Lee

Inventor： Kyoung-Ju Shin ,  Hye-Young Ryu ,  Jang-Soo Kim ,  Chong-Chul Chal ,  Jae-Hyoung Youn ,  Young-Wook Lee

IPC: G02F1/1335 ,  G02F1/1343

CPC classification number: G02F1/133514 ,  G02F1/134309 ,  G02F2001/134345 ,  G02F2001/136222

Abstract: A thin film transistor array panel includes a substrate, a first gate line and a second gate line formed on the substrate, a storage electrode line between the first gate line and the second gate line, a data line intersecting the first gate line and the second gate line, a first thin film transistor connected to the first gate line and the data line, at least one color filter formed on the first thin film transistor, wherein the color filter comprises a first portion adjacent the first gate line with respect to the storage electrode line, a second portion adjacent the second gate line with respect to the storage electrode line, and a first connection connecting the first portion and the second portion and having a narrower width than that of the first and second portions, a first sub-pixel electrode formed on the color filter and connected to the first thin film transistor, and a second sub-pixel electrode facing the first sub-pixel electrode with respect to a gap, wherein at least one of an edge of the first sub-pixel electrode and an edge of the second sub-pixel electrode crosses over the first connection of the color filter, the edge of the first sub-pixel electrode, and the edge of the second sub-pixel electrode defining the gap between the first sub-pixel electrode and the second sub-pixel electrode.

Abstract translation: 薄膜晶体管阵列面板包括基板，形成在基板上的第一栅极线和第二栅极线，在第一栅极线和第二栅极线之间的存储电极线，与第一栅极线和第二栅极线相交的数据线 栅极线，连接到第一栅极线和数据线的第一薄膜晶体管，形成在第一薄膜晶体管上的至少一个滤色器，其中滤色器包括相对于存储器的第一栅极线的第一部分 电极线，相对于存储电极线相邻于第二栅极线的第二部分，以及连接第一部分和第二部分并且具有比第一和第二部分窄的宽度的第一连接，第一子像素 电极，形成在滤色器上并连接到第一薄膜晶体管，第二子像素电极相对于间隙面对第一子像素电极，其中至少在 第一子像素电极的边缘和第二子像素电极的边缘的第二子像素电极的边缘与滤色器的第一连接，第一子像素电极的边缘和第二子像素电极的边缘交叉 限定第一子像素电极和第二子像素电极之间的间隙的电极。

公开(公告)号：US09287283B2

公开(公告)日：2016-03-15

申请号：US13462082

申请日：2012-05-02

Applicant: Se-Yun Lim ,  Eun-Seok Choi ,  Young-Wook Lee ,  Won-Joon Choi ,  Ki-Hong Lee ,  Sang-Bum Lee

Inventor： Se-Yun Lim ,  Eun-Seok Choi ,  Young-Wook Lee ,  Won-Joon Choi ,  Ki-Hong Lee ,  Sang-Bum Lee

IPC: H01L27/115

CPC classification number: H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582

Abstract: A method for fabricating a non-volatile memory device includes alternately stacking a plurality of interlayer dielectric layers and a plurality of conductive layers over a substrate, etching the interlayer dielectric layers and the conductive layers to form a trench which exposes a surface of the substrate forming a first material layer over a resulting structure in which the trench is formed, forming a second material layer over the first material layer, removing portions of the second material layer and the first material layer formed on a bottom of the trench to expose the surface of the substrate, removing the second material layer, and burying a channel layer within the trench in which the second material layer is removed.

Abstract translation: 一种用于制造非易失性存储器件的方法包括在衬底上交替堆叠多个层间电介质层和多个导电层，蚀刻层间电介质层和导电层以形成暴露衬底形成表面的沟槽 在其中形成沟槽的结果结构上的第一材料层，在第一材料层上形成第二材料层，去除第二材料层的部分和形成在沟槽的底部上的第一材料层，以暴露出 衬底，去除第二材料层，以及在去除第二材料层的沟槽内掩埋沟道层。

公开(公告)号：US08914679B2

公开(公告)日：2014-12-16

申请号：US11363725

申请日：2006-02-28

Applicant: Laura I. Apostoloiu ,  Xin Chen ,  R. Scott Harvey ,  Young Wook Lee ,  Kyle Robeson

Inventor： Laura I. Apostoloiu ,  Xin Chen ,  R. Scott Harvey ,  Young Wook Lee ,  Kyle Robeson

IPC: G06F11/00 ,  G06F11/36

CPC classification number: G06F11/3684 ,  G06F11/3664

Abstract: Embodiments of the present invention address deficiencies of the art in respect to software test automation and provide a method, system and apparatus for a reusable software testing framework. In one embodiment of the invention, an automated application test data processing system can include a reusable test automation framework. The system further can include a test task generator and a scenario generator coupled to one another and to the framework. In this regard, the test task generator can be configured to generate uniform logic for performing testing tasks, while the scenario generator can be configured to arrange testing tasks for a complete test scenario. Finally, a collaborative testing environment can be provided through which multiple users can interact with the scenario generator and test task generator to produce test cases of different test scenarios.

Abstract translation: 本发明的实施例解决了本领域在软件测试自动化方面的缺陷，并且提供了一种用于可重复使用的软件测试框架的方法，系统和装置。 在本发明的一个实施例中，自动应用测试数据处理系统可以包括可重用的测试自动化框架。 该系统还可以包括测试任务生成器和彼此耦合到框架的脚本生成器。 在这方面，测试任务生成器可以配置为生成用于执行测试任务的统一逻辑，而脚本生成器可以配置为为完整测试场景安排测试任务。 最后，可以提供协作测试环境，多个用户可以通过该环境与脚本生成器和测试任务生成器进行交互，以生成不同测试场景的测试用例。

公开(公告)号：US08624238B2

公开(公告)日：2014-01-07

申请号：US13004665

申请日：2011-01-11

Applicant: Jong-In Kim ,  Young-Wook Lee ,  Jean-Ho Song ,  Jae-Hyoung Yoon ,  Sung-Ryul Kim ,  Byeong-Beom Kim ,  Je-Hyeong Park ,  Woo-Geun Lee

Inventor： Jong-In Kim ,  Young-Wook Lee ,  Jean-Ho Song ,  Jae-Hyoung Yoon ,  Sung-Ryul Kim ,  Byeong-Beom Kim ,  Je-Hyeong Park ,  Woo-Geun Lee

IPC: H01L21/34 ,  H01L29/786

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L27/1288

Abstract: A thin-film transistor (TFT) substrate having reduced defects is fabricated using a reduced number of masks. The TFT substrate includes gate wiring formed on a substrate. The gate wiring includes a gate electrode. A semiconductor pattern is formed on the gate wiring. An etch-stop pattern is formed on the semiconductor pattern. Data wiring includes a source electrode which is formed on the semiconductor pattern and the etch-stop pattern. Each of the gate wiring and the data wiring includes a copper-containing layer and a buffer layer formed on or under the copper-containing layer.

Abstract translation: 使用减少数量的掩模制造具有减少的缺陷的薄膜晶体管（TFT）基板。 TFT基板包括形成在基板上的栅极布线。 栅极布线包括栅电极。 在栅极布线上形成半导体图形。 在半导体图案上形成蚀刻停止图案。 数据布线包括形成在半导体图案上的源电极和蚀刻停止图案。 栅极布线和数据布线中的每一个包括在含铜层上形成的含铜层和缓冲层。