公开(公告)号：US20080295605A1

公开(公告)日：2008-12-04

申请号：US12128159

申请日：2008-05-28

Applicant: YOUNG CHAN JANG ,  Jung-Bae Lee ,  Yun-Sang Lee

Inventor： YOUNG CHAN JANG ,  Jung-Bae Lee ,  Yun-Sang Lee

IPC: G01B7/16

CPC classification number: G01R31/2849 ,  G01R31/2621 ,  G01R31/2642 ,  G11C29/12 ,  G11C29/50

Abstract: A stress detection circuit includes a function block and a detection signal generation circuit. The function block outputs a first voltage such that the first voltage is varied depending on an extent that the function block is stressed. The detection signal generation circuit generates a stress detection signal based on the first voltage and a second voltage during a test mode. The stress detection signal represents integration of the function block, and a level of the second voltage corresponds to a level of the first voltage before the function block is stressed.

Abstract translation: 应力检测电路包括功能块和检测信号生成电路。 功能块输出第一电压，使得第一电压根据功能块受应力的程度而变化。 检测信号发生电路在测试模式期间产生基于第一电压和第二电压的应力检测信号。 应力检测信号表示功能块的积分，第二电压的电平对应于在功能块受到应力之前的第一电压的电平。

公开(公告)号：US20080159055A1

公开(公告)日：2008-07-03

申请号：US11875171

申请日：2007-10-19

Applicant: Yun-sang LEE ,  Jung-bae LEE

Inventor： Yun-sang LEE ,  Jung-bae LEE

IPC: G11C8/00

CPC classification number: G11C8/08

Abstract: A method and circuit are provided for driving a word line. The word line driving circuit includes first and second power drivers, a switching unit and a word line driver. The first power driver is driven to a boosting voltage level and the second power driver is driven to an internal power voltage level. The switching unit transfers a first output of the first power driver to the word line driver in response to a first switching signal and transfers a second output of the second power driver to the word line driver in response to a second switching signal. The word line driver alternately drives a word line to the first output and the second output transferred from the switching unit in response to a word line driving signal.

Abstract translation: 提供了用于驱动字线的方法和电路。 字线驱动电路包括第一和第二电源驱动器，开关单元和字线驱动器。 第一个功率驱动器被驱动到升压电压电平，第二个功率驱动器被驱动到内部电源电压电平。 切换单元响应于第一切换信号将第一功率驱动器的第一输出传送到字线驱动器，并响应于第二切换信号将第二功率驱动器的第二输出传送到字线驱动器。 字线驱动器响应于字线驱动信号交替地驱动字线到第一输出和从开关单元传送的第二输出。

公开(公告)号：US07313046B2

公开(公告)日：2007-12-25

申请号：US11214657

申请日：2005-08-30

Applicant: Sung-ho Choi ,  Yun-sang Lee

Inventor： Sung-ho Choi ,  Yun-sang Lee

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C11/40618

Abstract: A semiconductor memory device includes a plurality of memory banks. A refresh control block is responsive to a control address that identifies at least one of the plurality of memory banks to be refreshed. The refresh control block is configured to control refreshing of the at least one of the plurality of memory banks to be refreshed. The control address is used during read and/or write operations of the plurality of memory banks.

Abstract translation: 半导体存储器件包括多个存储体。 刷新控制块响应于识别要刷新的多个存储器组中的至少一个的控制地址。 刷新控制块被配置为控制要刷新的多个存储体中的至少一个的刷新。 在多个存储体的读取和/或写入操作期间使用控制地址。

公开(公告)号：US07274584B2

公开(公告)日：2007-09-25

申请号：US11330819

申请日：2006-01-11

Applicant: Dae-Hee Jung ,  Chul-Woo Park ,  Yun-Sang Lee

Inventor： Dae-Hee Jung ,  Chul-Woo Park ,  Yun-Sang Lee

IPC: G11C5/06

CPC classification number: G11C8/08

Abstract: Provided are a semiconductor memory device having a wordline enable signal line arrangement scheme, which can reduce VPP power consumption and can increase the speed of driving a sub-wordline, and a method of arranging wordline enable signal lines in the semiconductor memory device. In the semiconductor memory device, a wordline enable driver is arranged in a row decoder region outside a memory array region, and the wordline enable signal lines are formed of an uppermost metal layer among three metal layers constituting the semiconductor memory device. Each of the wordline enable signal lines is connected to a sub-wordline driver, rather than to a pair of sub-wordline drivers. In other words, the wordline enable signal lines vertically and horizontally extend forming an inverse L shape.

Abstract translation: 提供一种具有字线使能信号线布置方案的半导体存储器件，其可以降低VPP功耗并且可以提高驱动子字线的速度，以及在半导体存储器件中布置字线使能信号线的方法。 在半导体存储器件中，字线使能驱动器被布置在存储器阵列区域外的行解码器区域中，并且字线使能信号线由构成半导体存储器件的三个金属层中的最上面的金属层形成。 每个字线使能信号线都连接到子字线驱动器，而不是一对子字线驱动器。 换句话说，字线使能信号线垂直和水平地延伸形成倒L形。

公开(公告)号：US07196941B2

公开(公告)日：2007-03-27

申请号：US10798469

申请日：2004-03-11

Applicant: Yun-Sang Lee ,  Jung-Bae Lee ,  Jung-Hwan Choi

Inventor： Yun-Sang Lee ,  Jung-Bae Lee ,  Jung-Hwan Choi

IPC: G11C7/10

CPC classification number: G11C7/18 ,  G11C7/10 ,  G11C7/1021 ,  G11C7/1048 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2207/2281 ,  G11C2207/229

Abstract: A semiconductor memory device and a method for writing and reading data to and from the same comprises a memory cell array including a plurality of memory cells connected between a plurality of word lines and a plurality of bit line pairs, a predetermined number of write line pairs, a predetermined number of read line pairs, a plurality of write column selection gates for transmitting data between the plurality of bit line pairs and the predetermined number of write line pair during a write operation, and a plurality of read column selection gates for transmitting data between the plurality of bit line pairs and the predetermined number of read line pairs during a read operation. Accordingly, it is possible to input and output data simultaneously through data input pads and data output pads.

Abstract translation: 一种半导体存储器件和用于从其读取和读取数据的方法包括：存储单元阵列，包括连接在多个字线和多个位线对之间的多个存储器单元，预定数量的写入线对 ，预定数量的读线对，用于在写入操作期间在多个位线对与预定数量的写入线对之间传送数据的多个写入列选择门和用于发送数据的多个读取列选择门 在读取操作期间在多个位线对与预定数量的读取线对之间。 因此，可以通过数据输入焊盘和数据输出焊盘同时输入和输出数据。

公开(公告)号：US20060152992A1

公开(公告)日：2006-07-13

申请号：US11330819

申请日：2006-01-11

Applicant: Dae-Hee Jung ,  Chul-Woo Park ,  Yun-Sang Lee

Inventor： Dae-Hee Jung ,  Chul-Woo Park ,  Yun-Sang Lee

IPC: G11C8/00

CPC classification number: G11C8/08

Abstract: Provided are a semiconductor memory device having a wordline enable signal line arrangement scheme, which can reduce VPP power consumption and can increase the speed of driving a sub-wordline, and a method of arranging wordline enable signal lines in the semiconductor memory device. In the semiconductor memory device, a wordline enable driver is arranged in a row decoder region outside a memory array region, and the wordline enable signal lines are formed of an uppermost metal layer among three metal layers constituting the semiconductor memory device. Each of the wordline enable signal lines is connected to a sub-wordline driver, rather than to a pair of sub-wordline drivers. In other words, the wordline enable signal lines vertically and horizontally extend forming an inverse L shape.

Abstract translation: 提供一种具有字线使能信号线布置方案的半导体存储器件，其可以降低VPP功耗并且可以提高驱动子字线的速度，以及在半导体存储器件中布置字线使能信号线的方法。 在半导体存储器件中，字线使能驱动器被布置在存储器阵列区域外的行解码器区域中，并且字线使能信号线由构成半导体存储器件的三个金属层中的最上面的金属层形成。 每个字线使能信号线都连接到子字线驱动器，而不是一对子字线驱动器。 换句话说，字线使能信号线垂直和水平地延伸形成倒L形。

公开(公告)号：US06868034B2

公开(公告)日：2005-03-15

申请号：US10639858

申请日：2003-08-13

Applicant: One-Gyun La ,  Yun-Sang Lee

Inventor： One-Gyun La ,  Yun-Sang Lee

IPC: G11C8/08 ,  G11C7/10 ,  G11C8/14 ,  G11C11/408 ,  G11C29/28 ,  G11C8/00

CPC classification number: G11C29/28 ,  G11C7/1021 ,  G11C7/1045 ,  G11C8/14 ,  G11C11/4085 ,  G11C11/4087 ,  G11C2029/1202 ,  G11C2029/1804

Abstract: A semiconductor memory device having an architecture that allows a user to change a page length of the semiconductor device. Circuits and methods for changing a page length of a semiconductor device enable selective activation of one or more corresponding wordlines (having the same row address) of memory cell array blocks of a memory cell array to thereby change the page length according to a specified operational mode.

Abstract translation: 一种具有允许用户改变半导体器件的寻址长度的架构的半导体存储器件。 用于改变半导体器件的页面长度的电路和方法使得能够选择性地激活存储器单元阵列的存储器单元阵列块的一个或多个对应字线（具有相同行地址），从而根据指定的操作模式改变页长度 。

公开(公告)号：US06459636B2

公开(公告)日：2002-10-01

申请号：US09838358

申请日：2001-04-19

Applicant: Yun-Sang Lee ,  Sang-Seok Kang ,  Kyu-Nam Lim ,  Jong-Hyun Choi

Inventor： Yun-Sang Lee ,  Sang-Seok Kang ,  Kyu-Nam Lim ,  Jong-Hyun Choi

IPC: G11C700

CPC classification number: G11C29/46

Abstract: A mode selection circuit for a semiconductor memory device includes a timing register for generating first and second control signals in response to a command signal and a first address signal, a programming control signal generator for generating third control signals in response to a second address signal and the first control signal, and a mode selection signal generator for generating mode selection signals in response to a master signal, the second control signal, and the third control signals, wherein the mode selection signals are activated in accordance with a sequential order of activation of the third control signals.

公开(公告)号：US06438047B1

公开(公告)日：2002-08-20

申请号：US09908192

申请日：2001-07-18

Applicant: Yun-Sang Lee ,  Jong-Hyun Choi ,  Sang-Suk Kang ,  Kyu-Nam Lim

Inventor： Yun-Sang Lee ,  Jong-Hyun Choi ,  Sang-Suk Kang ,  Kyu-Nam Lim

IPC: G11C700

CPC classification number: G11C29/846

Abstract: A semiconductor memory device comprises a memory cell array, at least one redundant cell control, a sense amplifier, and at least one redundant cell. The memory cell array receives and outputs data through data I/O line groups. The redundant cell control stores a defective cell address, generates a redundant cell enable control signal when the defective cell address is equal to an input cell address, generates a redundant cell read control signal during a read operation in response to the redundant cell enable control signal, and generates a redundant cell write control signal during a write operation in response to the redundant cell enable control signal. The sense amplifier is connected to an I/O line group commonly connected to the data I/O line groups, amplifies and outputs data outputted from the memory cell array during the read operation, and is disabled in response to the redundant cell read control signal. The redundant cell stores input data transferred to the I/O line group in response to the redundant cell write control signal and outputs stored data in response to the redundant cell read control signal.

Abstract translation: 半导体存储器件包括存储单元阵列，至少一个冗余单元控制，读出放大器和至少一个冗余单元。 存储单元阵列通过数据I / O线组接收和输出数据。 冗余单元控制存储故障单元地址，当缺陷单元地址等于输入单元地址时产生冗余单元使能控制信号，在读操作期间响应冗余单元使能控制信号产生冗余单元读控制信号 并且响应于冗余单元使能控制信号在写操作期间产生冗余单元写入控制信号。 感测放大器连接到通常连接到数据I / O线组的I / O线组，在读操作期间放大并输出从存储单元阵列输出的数据，并响应于冗余单元读取控制信号而被禁止 。 冗余单元响应于冗余单元写入控制信号存储传送到I / O线组的输入数据，并根据冗余单元读取控制信号输出存储的数据。

公开(公告)号：US06392938B1

公开(公告)日：2002-05-21

申请号：US09955635

申请日：2001-09-19

Applicant: Jong-Hyun Choi ,  Sang-Seok Kang ,  Yun-Sang Lee

Inventor： Jong-Hyun Choi ,  Sang-Seok Kang ,  Yun-Sang Lee

IPC: G11C700

CPC classification number: G11C29/785

Abstract: A semiconductor memory device comprises a memory cell array, a defective address programming means, a redundant enable signal generating means, an output means, and a mode control signal setting means. The memory cell array comprises a plurality of memory cells. The defective address programming means programs a redundant control signal and a defective address of a defective memory cell among the plurality of the memory cells at a package level in response to a first control signal and an address signal applied from an external portion. The redundant enable signal generating means generates a comparison coincident signal in response to the redundant control signal when the address is consistent with the defective address. The output means outputs the comparison coincident signal to an external portion in response to a second control signal during a test operation. The mode control signal setting means sets a state of the first and second control signals in response to a command signal and a mode setting signal applied from an external portion.

Abstract translation: 半导体存储器件包括存储单元阵列，缺陷地址编程装置，冗余使能信号发生装置，输出装置和模式控制信号设置装置。 存储单元阵列包括多个存储单元。 缺陷地址编程装置响应于从外部施加的第一控制信号和地址信号，以封装级别编程多个存储器单元中的有缺陷的存储单元的冗余控制信号和缺陷地址。 当地址与缺陷地址一致时，冗余使能信号发生装置响应于冗余控制信号产生比较重合信号。 输出装置在测试操作期间响应于第二控制信号将比较重合信号输出到外部部分。 模式控制信号设置装置响应于从外部施加的命令信号和模式设置信号来设置第一和第二控制信号的状态。