公开(公告)号：US07274584B2

公开(公告)日：2007-09-25

申请号：US11330819

申请日：2006-01-11

申请人： Dae-Hee Jung ,  Chul-Woo Park ,  Yun-Sang Lee

发明人： Dae-Hee Jung ,  Chul-Woo Park ,  Yun-Sang Lee

IPC分类号： G11C5/06

CPC分类号： G11C8/08

摘要： Provided are a semiconductor memory device having a wordline enable signal line arrangement scheme, which can reduce VPP power consumption and can increase the speed of driving a sub-wordline, and a method of arranging wordline enable signal lines in the semiconductor memory device. In the semiconductor memory device, a wordline enable driver is arranged in a row decoder region outside a memory array region, and the wordline enable signal lines are formed of an uppermost metal layer among three metal layers constituting the semiconductor memory device. Each of the wordline enable signal lines is connected to a sub-wordline driver, rather than to a pair of sub-wordline drivers. In other words, the wordline enable signal lines vertically and horizontally extend forming an inverse L shape.

摘要翻译： 提供一种具有字线使能信号线布置方案的半导体存储器件，其可以降低VPP功耗并且可以提高驱动子字线的速度，以及在半导体存储器件中布置字线使能信号线的方法。 在半导体存储器件中，字线使能驱动器被布置在存储器阵列区域外的行解码器区域中，并且字线使能信号线由构成半导体存储器件的三个金属层中的最上面的金属层形成。 每个字线使能信号线都连接到子字线驱动器，而不是一对子字线驱动器。 换句话说，字线使能信号线垂直和水平地延伸形成倒L形。

公开(公告)号：US20060152992A1

公开(公告)日：2006-07-13

申请号：US11330819

申请日：2006-01-11

申请人： Dae-Hee Jung ,  Chul-Woo Park ,  Yun-Sang Lee

发明人： Dae-Hee Jung ,  Chul-Woo Park ,  Yun-Sang Lee

IPC分类号： G11C8/00

CPC分类号： G11C8/08

摘要： Provided are a semiconductor memory device having a wordline enable signal line arrangement scheme, which can reduce VPP power consumption and can increase the speed of driving a sub-wordline, and a method of arranging wordline enable signal lines in the semiconductor memory device. In the semiconductor memory device, a wordline enable driver is arranged in a row decoder region outside a memory array region, and the wordline enable signal lines are formed of an uppermost metal layer among three metal layers constituting the semiconductor memory device. Each of the wordline enable signal lines is connected to a sub-wordline driver, rather than to a pair of sub-wordline drivers. In other words, the wordline enable signal lines vertically and horizontally extend forming an inverse L shape.

摘要翻译： 提供一种具有字线使能信号线布置方案的半导体存储器件，其可以降低VPP功耗并且可以提高驱动子字线的速度，以及在半导体存储器件中布置字线使能信号线的方法。 在半导体存储器件中，字线使能驱动器被布置在存储器阵列区域外的行解码器区域中，并且字线使能信号线由构成半导体存储器件的三个金属层中的最上面的金属层形成。 每个字线使能信号线都连接到子字线驱动器，而不是一对子字线驱动器。 换句话说，字线使能信号线垂直和水平地延伸形成倒L形。

公开(公告)号：US09183910B2

公开(公告)日：2015-11-10

申请号：US13907223

申请日：2013-05-31

申请人： Yun-Sang Lee ,  Dong-Seok Kang ,  Sang-Beom Kang ,  Chan-Kyung Kim ,  Chul-Woo Park ,  Dong-Hyun Sohn ,  Hyung-Rok Oh

发明人： Yun-Sang Lee ,  Dong-Seok Kang ,  Sang-Beom Kang ,  Chan-Kyung Kim ,  Chul-Woo Park ,  Dong-Hyun Sohn ,  Hyung-Rok Oh

IPC分类号： G11C11/16 ,  G11C7/12

CPC分类号： G11C11/1653 ,  G11C7/12 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/1697

摘要： A semiconductor memory device includes a cell array including one or more bank groups, where each of the one or more bank groups includes a plurality of banks and each of the plurality of banks includes a plurality of spin transfer torque magneto resistive random access memory (STT-MRAM) cells. The semiconductor memory device further includes a source voltage generating unit for applying a voltage to a source line connected to the each of the plurality of STT-MRAM cells, and a command decoder for decoding a command from an external source in order to perform read and write operations on the plurality of STT-MRAM cells. The command includes a combination of at least one signal of a row address strobe (RAS), a column address strobe (CAS), a chip selecting signal (CS), a write enable signal (WE), and a clock enable signal (CKE).

摘要翻译： 半导体存储器件包括一个单元阵列，其包括一个或多个存储体组，其中一个或多个存储体组中的每个组包括多个存储体，并且多个存储体中的每一个存储体包括多个自旋传递转矩磁阻随机存取存储器（STT -MRAM）细胞。 半导体存储器件还包括用于向连接到多个STT-MRAM单元中的每一个的源极线施加电压的源极电压产生单元，以及用于对来自外部源的命令进行解码的命令解码器，以执行读取和 对多个STT-MRAM单元进行写入操作。 该命令包括行地址选通（RAS），列地址选通（CAS），片选信号（CS），写使能信号（WE）和时钟使能信号（CKE）的至少一个信号 ）。

公开(公告)号：US09171589B2

公开(公告)日：2015-10-27

申请号：US13705143

申请日：2012-12-04

申请人： Chan-Kyung Kim ,  Yun-Sang Lee ,  Chul-Woo Park ,  Hong-Sun Hwang

发明人： Chan-Kyung Kim ,  Yun-Sang Lee ,  Chul-Woo Park ,  Hong-Sun Hwang

IPC分类号： G11C16/04 ,  G11C7/06 ,  G11C13/00 ,  G11C11/16 ,  G11C16/26

CPC分类号： G11C7/06 ,  G11C7/065 ,  G11C7/222 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/4076 ,  G11C11/4091 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/26 ,  G11C16/28 ,  G11C27/02 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2213/71 ,  H01L27/222 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06

摘要： Provided is a memory device having a first switch configured to receive a first CSL signal to input or output data. A second switch is configured to receive a second CSL signal. A sensing and latch circuit (SLC) is coupled between the first and second switches. And at least one memory cell is coupled to the second switch. The second switch is configured to control timing of read or write operations of the at least one memory cell in response to the second CSL signal, e.g., where a read operation can be performed in not more than about 5 ns. The SLC operates as a latch in a write mode and as an amplifier in a read mode. The memory device may comprise part of a memory system or other apparatus including such memory device or system. Methods of performing read and write operations using such memory device are also provided.

摘要翻译： 提供了一种存储器件，其具有被配置为接收第一CSL信号以输入或输出数据的第一开关。 第二开关被配置为接收第二CSL信号。 感测和锁存电路（SLC）耦合在第一和第二开关之间。 并且至少一个存储器单元耦合到第二开关。 第二开关被配置为响应于第二CSL信号来控制至少一个存储器单元的读取或写入操作的定时，例如，可以在不超过约5ns的范围内执行读取操作。 SLC作为写入模式的锁存器和读取模式下的放大器工作。 存储器装置可以包括存储器系统的一部分或包括这种存储器装置或系统的其他装置。 还提供了使用这种存储器件执行读和写操作的方法。

公开(公告)号：US20130148429A1

公开(公告)日：2013-06-13

申请号：US13705143

申请日：2012-12-04

申请人： Chan-Kyung Kim ,  Yun-Sang Lee ,  Chul-Woo Park ,  Hong-Sun Hwang

发明人： Chan-Kyung Kim ,  Yun-Sang Lee ,  Chul-Woo Park ,  Hong-Sun Hwang

IPC分类号： G11C7/06 ,  G11C11/16 ,  G11C16/26 ,  G11C13/00

CPC分类号： G11C7/06 ,  G11C7/065 ,  G11C7/222 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/4076 ,  G11C11/4091 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C16/26 ,  G11C16/28 ,  G11C27/02 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2213/71 ,  H01L27/222 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06

摘要： Provided is a memory device having a first switch configured to receive a first CSL signal to input or output data. A second switch is configured to receive a second CSL signal. A sensing and latch circuit (SLC) is coupled between the first and second switches. And at least one memory cell is coupled to the second switch. The second switch is configured to control timing of read or write operations of the at least one memory cell in response to the second CSL signal, e.g., where a read operation can be performed in not more than about 5 ns. The SLC operates as a latch in a write mode and as an amplifier in a read mode. The memory device may comprise part of a memory system or other apparatus including such memory device or system. Methods of performing read and write operations using such memory device are also provided.

摘要翻译： 提供了一种存储器件，其具有被配置为接收第一CSL信号以输入或输出数据的第一开关。 第二开关被配置为接收第二CSL信号。 感测和锁存电路（SLC）耦合在第一和第二开关之间。 并且至少一个存储器单元耦合到第二开关。 第二开关被配置为响应于第二CSL信号来控制至少一个存储器单元的读取或写入操作的定时，例如，可以在不超过约5ns的范围内执行读取操作。 SLC作为写入模式的锁存器和读取模式下的放大器工作。 存储器装置可以包括存储器系统的一部分或包括这种存储器装置或系统的其他装置。 还提供了使用这种存储器件执行读和写操作的方法。

公开(公告)号：US20080080285A1

公开(公告)日：2008-04-03

申请号：US11730275

申请日：2007-03-30

申请人： Jung Sunwoo ,  Yun-Sang Lee ,  Hoe-Ju Chung

发明人： Jung Sunwoo ,  Yun-Sang Lee ,  Hoe-Ju Chung

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40618

摘要： A refresh method for a semiconductor memory device having more than one bank group is provided. The refresh method may include applying an all-refresh command to one the bank groups, determining if one of the bank groups includes a bank undergoing a refresh operation when the all-refresh command is received, and performing an all-refresh operation based on the determination.

摘要翻译： 提供了具有多于一个组组的半导体存储器件的刷新方法。 刷新方法可以包括：将全刷新命令应用于银行组中的一个，当接收到全刷新命令时，确定银行组中的一个是否包括经历刷新操作的存储体，并且基于所述刷新操作执行全刷新操作 决心。

公开(公告)号：US20060044912A1

公开(公告)日：2006-03-02

申请号：US11129073

申请日：2005-05-13

申请人： Byoung-Sul Kim ,  Yun-Sang Lee

发明人： Byoung-Sul Kim ,  Yun-Sang Lee

IPC分类号： G11C7/00

CPC分类号： G11C7/1042 ,  G11C11/406 ,  G11C11/40618

摘要： For refreshing a memory device, a refresh selection unit is enabled within a selected group of memory cells for refreshing at least one memory cell within the selected group in response to a refresh control signal and a refresh address signal from an external source. In addition, a normal operation circuit performs a normal operation on at least one memory cell of another group of memory cells while the at least one memory cell within the selected group is being refreshed to reduce refresh overhead.

摘要翻译： 为了刷新存储器件，刷新选择单元在所选择的存储器单元组内启用，用于响应于来自外部源的刷新控制信号和刷新地址信号刷新所选组中的至少一个存储器单元。 此外，正常操作电路对另一组存储器单元的至少一个存储单元执行正常操作，同时刷新所选组内的至少一个存储单元以减少刷新开销。

公开(公告)号：US06996754B1

公开(公告)日：2006-02-07

申请号：US09672223

申请日：2000-09-27

申请人： Yun-Sang Lee

发明人： Yun-Sang Lee

IPC分类号： G01R31/28

CPC分类号： G11C29/48 ,  G11C29/1201

摘要： An integrated circuit device for testing is disclosed. The device includes a plurality of internal circuits for generating a plurality of internal signals, the internal signals used for addressing storage locations and for controlling internal operations, a first selection circuit for receiving the internal circuits in response to selection signals corresponding to test information signals, a second selection circuit for receiving output signals from the first selection circuit and output signals from a sense amplifier, and for opening an alternative one of transfer paths of the internal signals and the output signals in response to the selection signals, and a data output buffer for transferring output signals from the second selection signals to an outside of the device through data input/output pads.

摘要翻译： 公开了一种用于测试的集成电路装置。 该装置包括用于产生多个内部信号的多个内部电路，用于寻址存储位置和用于控制内部操作的内部信号，用于响应于与测试信息信号对应的选择信号接收内部电路的第一选择电路， 第二选择电路，用于接收来自第一选择电路的输出信号和来自读出放大器的输出信号，以及响应于选择信号打开内部信号和输出信号的传输路径中的另一个传输路径;以及数据输出缓冲器 用于通过数据输入/输出焊盘将输出信号从第二选择信号传送到设备的外部。

公开(公告)号：US20050243627A1

公开(公告)日：2005-11-03

申请号：US11105169

申请日：2005-04-12

申请人： Yun-Sang Lee ,  Jung-Bae Lee

发明人： Yun-Sang Lee ,  Jung-Bae Lee

IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C11/406

CPC分类号： G11C11/40611 ,  G11C11/406 ,  G11C11/40618

摘要： Method and apparatus for use with multi-bank Synchronous Dynamic Random Access Memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a current refresh row. When all bank addresses have been supplied for the current row, the SDRAM circuit updates the current refresh row and repeats the process. This process can allow a memory controller to modify an auto-refresh bank sequence as necessary such that auto-refresh operations can proceed on some memory banks concurrently with reads and writes to other memory banks, allowing better utilization of the SDRAM circuit. Other embodiments are described and claimed.

摘要翻译： 公开了用于多存储体同步动态随机存取存储器（SDRAM）电路，模块和存储器系统的方法和装置。 在一个描述的实施例中，SDRAM电路接收要在自动刷新操作中使用的存储体地址，并对指定的存储体和当前刷新行执行自动刷新操作。 当所有存储体地址已被提供给当前行时，SDRAM电路更新当前刷新行并重复该过程。 该过程可以允许存储器控制器根据需要修改自动刷新存储体序列，使得自动刷新操作可以在一些存储体上与对其它存储体的读取和写入同时进行，从而更好地利用SDRAM电路。 描述和要求保护其他实施例。

公开(公告)号：US06775170B2

公开(公告)日：2004-08-10

申请号：US10222110

申请日：2002-08-16

申请人： Yun-Sang Lee ,  Won-Chang Jung

发明人： Yun-Sang Lee ,  Won-Chang Jung

IPC分类号： G11C702

CPC分类号： G11C7/02 ,  G11C7/1048 ,  G11C2207/002

摘要： A semiconductor memory device comprises a write column select line or read column select line for shielding a signal line. The semiconductor memory device may include a signal line, a read column select line, and a write column select line. The signal line may transmit an operation signal related to the operation of the semiconductor memory device. The read column select line may transmit a read column select signal, which may control transfer of a data signal of a bit line to a data line. The write column select line may transmit a write column select signal, which may control transfer of the data signal of the data line to the bit line. One of the read column select line and the write column select line to transmit a deactivated column select signal among the read column select signal and the write column select signal, may be maintained at a predetermined logic level and may shield the signal line.

摘要翻译： 半导体存储器件包括用于屏蔽信号线的写入列选择线或读取列选择线。 半导体存储器件可以包括信号线，读取列选择线和写入列选择线。 信号线可以发送与半导体存储器件的操作相关的操作信号。 读列选择线可以发送读列选择信号，其可以控制位线的数据信号到数据线的传送。 写列选择线可以发送写列选择信号，其可以控制数据线的数据信号到位线的传送。 在读列选择信号和写列选择信号之间读取列选择线和写列选择线之一发送去激活的列选择信号可以保持在预定的逻辑电平并且可以屏蔽信号线。