公开(公告)号：US20180165214A1

公开(公告)日：2018-06-14

申请号：US15377537

申请日：2016-12-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Amin Farmahini Farahani ,  David A. Roberts

IPC: G06F12/0888 ,  G06F12/0806

Abstract: A processing system fills a memory access request for data from a processor core by bypassing a cache when a write congestion condition is detected, and when transferring the data to the cache would cause eviction of a dirty cache line. The cache is bypassed by transferring the requested data to the processor core or to a different cache. Accordingly, the processing system can temporarily bypass the cache storing the dirty cache line when filling a memory access request, thereby avoiding the eviction and write back to main memory of a dirty cache line when a write congestion condition exists.

公开(公告)号：US09983655B2

公开(公告)日：2018-05-29

申请号：US14963352

申请日：2015-12-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Mitesh R. Meswani ,  David A. Roberts ,  Dmitri Yudanov ,  Arkaprava Basu ,  Sergey Blagodurov

IPC: G06F1/00 ,  G06F1/32 ,  G06F9/38

CPC classification number: G06F1/3243 ,  G06F9/3885

Abstract: A method and apparatus for performing inter-lane power management includes de-energizing one or more execution lanes upon a determination that the one or more execution lanes are to be predicated. Energy from the predicated execution lanes is redistributed to one or more active execution lanes.

公开(公告)号：US20180081563A1

公开(公告)日：2018-03-22

申请号：US15272894

申请日：2016-09-22

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: G06F3/06

CPC classification number: G11C7/00 ,  G11C7/222 ,  G11C2029/0409

Abstract: Logic such as a memory controller writes primary data from an incoming write request as well as corresponding replicated primary data (which is a copy of the primary data) to one or more different memory banks of random access memory in response to determining a memory access contention condition for the address (including a range of addresses) corresponding to the incoming write request. When the memory bank containing the primary data is busy servicing a write request, such as to another row of memory in the bank, a read request for the primary data is serviced by reading the replicated primary data from the different memory bank of the random access memory to service the incoming read request.

公开(公告)号：US20170277441A1

公开(公告)日：2017-09-28

申请号：US15331270

申请日：2016-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Gupta ,  David A. Roberts ,  Mitesh R. Meswani ,  Vilas Sridharan ,  Steven Raasch ,  Daniel I. Lowell

IPC: G06F3/06

CPC classification number: G06F12/02

Abstract: Techniques for selecting one of a plurality of heterogeneous memory units for placement of blocks of data (e.g., memory pages), based on both reliability and performance, are disclosed. A “cost” for each data block/memory unit combination is determined, based on the frequency of access of the data block, the latency of the memory unit, and, optionally, an architectural vulnerability factor (which represents the level of exposure of a particular memory data value to memory faults such as bit flips). A memory unit is selected for the data block for which the determined cost is the lowest, out of all memory units considered, and the data block is placed into that memory unit.

公开(公告)号：US09639280B2

公开(公告)日：2017-05-02

申请号：US14743091

申请日：2015-06-18

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: G06F12/00 ,  G06F3/06 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0679 ,  G06F3/0688

Abstract: The disclosed embodiments provide a system for processing a memory command on a computer system. During operation, a command scheduler executing on a memory controller of the computer system obtains a predicted latency of the memory command based on a memory address to be accessed by the memory command. Next, the command scheduler orders the memory command with other memory commands in a command queue for subsequent processing by a memory resource on the computer system based on the predicted latency of the memory command.

公开(公告)号：US20170085472A1

公开(公告)日：2017-03-23

申请号：US14859844

申请日：2015-09-21

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Michael Ignatowski ,  Nuwan Jayasena ,  Gabriel H. Loh

IPC: H04L12/781 ,  H04L12/715 ,  H04L12/861 ,  H04L29/06

CPC classification number: H04L45/52 ,  H04L45/04 ,  H04L49/9057 ,  H04L69/08

Abstract: A communication device includes a data source that generates data for transmission over a bus, and a data encoder that receives and encodes outgoing data. An encoder system receives outgoing data from a data source and stores the outgoing data in a first queue. An encoder encodes outgoing data with a header type that is based upon a header type indication from a controller and stores the encoded data that may be a packet or a data word with at least one layered header in a second queue for transmission. The device is configured to receive at a payload extractor, a packet protocol change command from the controller and to remove the encoded data and to re-encode the data to create a re-encoded data packet and placing the re-encoded data packet in the second queue for transmission.

公开(公告)号：US20170048320A1

公开(公告)日：2017-02-16

申请号：US15221554

申请日：2016-07-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Amin Farmahini-Farahani ,  David A. Roberts

IPC: H04L29/08 ,  G06F3/06

CPC classification number: H04L67/1097

Abstract: Devices, methods, and systems for distributed gather and scatter operations in a network of memory nodes. A responding memory node includes a memory; a communications interface having circuitry configured to communicate with at least one other memory node; and a controller. The controller includes circuitry configured to receive a request message from a requesting node via the communications interface. The request message indicates a gather or scatter operation, and instructs the responding node to retrieve data elements from a source memory data structure and store the data elements to a destination memory data structure. The controller further includes circuitry configured to transmit a response message to the requesting node via the communications interface. The response message indicates that the data elements have been stored into the destination memory data structure.

Abstract translation: 在内存节点网络中进行分布式收集和分散操作的设备，方法和系统。 响应存储器节点包括存储器; 通信接口，其具有被配置为与至少一个其他存储器节点进行通信的电路; 和控制器。 控制器包括经配置以经由通信接口从请求节点接收请求消息的电路。 请求消息指示收集或散布操作，并指示响应节点从源存储器数据结构中检索数据元素，并将数据元素存储到目的地存储器数据结构。 控制器还包括经配置以经由通信接口向请求节点发送响应消息的电路。 响应消息指示数据元素已被存储到目的地存储器数据结构中。

公开(公告)号：US20160371187A1

公开(公告)日：2016-12-22

申请号：US14746610

申请日：2015-06-22

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: G06F12/08 ,  G11C7/10 ,  G06F12/06

CPC classification number: G06F12/0862 ,  G06F12/0638 ,  G06F12/0811 ,  G06F12/0835 ,  G06F2212/1016 ,  G06F2212/205 ,  G06F2212/502 ,  G06F2212/602 ,  G06F2212/6022 ,  G06F2212/6024 ,  G06F2212/6026 ,  G06F2212/6028 ,  G06F2212/621

Abstract: A plurality of memory modules, which may be used to form a heterogeneous memory system, are connected to a plurality of prefetchers. Each prefetcher is independently configured to prefetch information from a corresponding one of the plurality of memory modules in response to feedback from the corresponding one of the plurality of memory modules.

Abstract translation: 可以用于形成异构存储器系统的多个存储器模块连接到多个预取器。 每个预取器被独立地配置为响应于来自多个存储器模块中的对应的一个的反馈而从多个存储器模块中的对应的一个存储器模块预取信息。

公开(公告)号：US09472299B2

公开(公告)日：2016-10-18

申请号：US14257919

申请日：2014-04-21

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts ,  Michael Ignatowski

IPC: G11C7/00 ,  G11C16/34 ,  G11C11/56 ,  G11C13/00

CPC classification number: G11C16/3418 ,  G11C11/56 ,  G11C11/5642 ,  G11C13/0033 ,  G11C13/004

Abstract: A memory cell is read by measuring a parameter associated with the memory cell with a first resolution to determine a value stored in the memory cell. The parameter is also measured with a second resolution that is finer than the first resolution. The memory cell is reprogrammed to mitigate an offset between the parameter as measured with the second resolution and the parameter as measured with the first resolution.

Abstract translation: 通过用第一分辨率测量与存储器单元相关联的参数来读取存储单元，以确定存储在存储单元中的值。 该参数也用比第一分辨率更精细的第二分辨率来测量。 重新编程存储器单元以减轻用第二分辨率测量的参数与用第一分辨率测量的参数之间的偏移。

公开(公告)号：US20150293812A1

公开(公告)日：2015-10-15

申请号：US14253638

申请日：2014-04-15

Applicant: Advanced Micro Devices, Inc.

Inventor： David A. Roberts

IPC: G06F11/10 ,  G11C29/04 ,  G11C29/52

CPC classification number: G11C29/04 ,  G06F11/1048 ,  G11C11/1673 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A memory read operation is directed at a group of semiconductor devices from which a first semiconductor device has been removed. An error in data for the memory read operation is detected based on error-correction coding (ECC). The error is caused at least in part by the first semiconductor device having been removed. ECC is used to determine corrected data for the memory read operation.

Abstract translation: 存储器读取操作指向已经从其移除第一半导体器件的一组半导体器件。 基于纠错编码（ECC）检测存储器读取操作的数据中的错误。 该误差至少部分地由第一半导体器件被去除。 ECC用于确定用于存储器读取操作的校正数据。