-
公开(公告)号：US09412465B2
公开(公告)日：2016-08-09
申请号：US14821254
申请日：2015-08-07
Applicant: Apple Inc.
Inventor： Yoav Kasorla , Shai Ojalvo , Eyal Gurgi
CPC classification number: G11C17/18 , G06F11/1044 , G11C17/16 , G11C29/74 , G11C29/787
Abstract: An integrated circuit includes fuse readout logic and first and second sets of fuses. One of the sets includes one or more primary fuses whose burn states represent respective bit values, and the other of the sets includes one or more secondary fuses whose burn states are indicative of the bit values stored in the primary fuses. The fuse readout logic is configured to read the bit values by sensing the burn states of the primary fuses, and to conditionally correct the read bit values by sensing the burn states of one or more of the secondary fuses.
-
52.发明授权Identifying word-line-to-substrate and word-line-to-word-line short-circuit events in a memory block 有权识别存储器块中的字线到基板和字线到字线的短路事件公开(公告)号：US09330783B1
公开(公告)日：2016-05-03
申请号：US14572818
申请日：2014-12-17
Applicant: APPLE INC.
Inventor： Barak Rotbard , Avraham Poza Meir , Eyal Gurgi , Yael Shur , Barak Baum
CPC classification number: G11C29/025 , G11C29/006 , G11C2029/1202
Abstract: An apparatus includes a memory and a memory controller. The memory includes a memory block that includes memory cells connected by word lines. The memory controller is configured to store data in the memory cells, and to identify a suspected short-circuit event in the memory block by recognizing a deviation of a performance characteristic of at least a given word line in the memory block relative to the performance characteristic of remaining word lines in the memory block.
Abstract translation: 一种装置包括存储器和存储器控制器。 该存储器包括一个包含通过字线连接的存储器单元的存储块。 存储器控制器被配置为将数据存储在存储器单元中，并且通过识别存储器块中的至少给定字线的性能特性相对于性能特性的偏差来识别存储器块中的可疑短路事件 剩余字线在存储器块中。
-
53.发明授权Mitigating reliability degradation of analog memory cells during long static and erased state retention 有权在长静态和擦除状态保持期间，减轻模拟存储单元的可靠性降级公开(公告)号：US09236132B2
公开(公告)日：2016-01-12
申请号：US14249448
申请日：2014-04-10
Applicant: Apple Inc.
Inventor： Yael Shur , Yoav Kasorla , Moshe Neerman , Naftali Sommer , Avraham Poza Meir , Etai Zaltsman , Eyal Gurgi , Meir Dalal
CPC classification number: G11C16/14 , G11C11/5628 , G11C16/0483 , G11C16/16 , G11C16/3418 , G11C16/349
Abstract: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.
Abstract translation: 一种非易失性存储器中的方法，其包括使用包括擦除级别的预定义编程级别集存储数据的多个存储器单元，包括接收指示要保留的一组存储器单元的存储操作，而不进行编程 长时间 组中的存储单元设置为与擦除级别不同的保留编程级别。 在准备使用数据对存储器单元组进行编程时，存储器单元组被擦除到擦除的电平，然后将数据编程在存储器单元组中。
-
54.发明申请公开(公告)号：US20150348632A1
公开(公告)日：2015-12-03
申请号：US14822992
申请日：2015-08-11
Applicant: Apple Inc.
Inventor： Avraham Poza Meir , Eyal Gurgi , Naftali Sommer , Yoav Kasorla
CPC classification number: G11C16/10 , G11C11/5671 , G11C16/0466 , G11C16/3418 , G11C16/3427
Abstract: A method includes, in a plurality of memory cells that share a common isolation layer and store in the common isolation layer quantities of electrical charge representative of data values, assigning a first group of the memory cells for data storage, and assigning a second group of the memory cells for protecting the electrical charge stored in the first group from retention drift. Data is stored in the memory cells of the first group. Protective quantities of the electrical charge that protect from the retention drift in the memory cells of the first group are stored in the memory cells of the second group.
Abstract translation: 一种方法包括在共享公共隔离层并存储在公共隔离层中的代表数据值的电荷量的多个存储器单元中，分配用于数据存储的第一组存储器单元，以及分配第二组 用于保护存储在第一组中的电荷的存储单元不保持漂移。 数据存储在第一组的存储单元中。 防止第一组的存储单元中保持漂移的电荷的保护量被存储在第二组的存储单元中。
-
公开(公告)号：US09136012B1
公开(公告)日：2015-09-15
申请号：US14269833
申请日：2014-05-05
Applicant: Apple Inc.
Inventor： Yoav Kasorla , Shai Ojalvo , Eyal Gurgi
CPC classification number: G11C17/18 , G06F11/1044 , G11C17/16 , G11C29/74 , G11C29/787
Abstract: An integrated circuit includes fuse readout logic and first and second sets of fuses. One of the sets includes one or more primary fuses whose burn states represent respective bit values, and the other of the sets includes one or more secondary fuses whose burn states are indicative of the bit values stored in the primary fuses. The fuse readout logic is configured to read the bit values by sensing the burn states of the primary fuses, and to conditionally correct the read bit values by sensing the burn states of one or more of the secondary fuses.
Abstract translation: 集成电路包括熔丝读出逻辑和第一和第二组保险丝。 其中一个集合包括一个或多个主熔丝，其燃烧状态表示相应的位值，并且这些组中的另一个包括一个或多个辅助熔丝，其燃烧状态指示存储在主熔丝中的位值。 熔丝读出逻辑被配置为通过感测主熔丝的燃烧状态来读取位值，并且通过感测一个或多个次熔丝的燃烧状态来有条件地校正读取位值。
-
Patent Agency Ranking
公开(公告)号：US09122403B2
公开(公告)日：2015-09-01
申请号：US13897944
申请日：2013-05-20
Applicant: Apple Inc.
Inventor： Eyal Gurgi , Micha Anholt , Yoav Kasorla
CPC classification number: G11C16/3427 , G06F3/0614 , G06F3/0653 , G06F3/0673 , G06F12/0238 , G06F12/0246 , G06F2212/1044 , G06F2212/7203 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/3431
Abstract: A method in a memory that includes multiple analog memory cells arranged in a three-dimensional (3-D) configuration, includes identifying multiple groups of potentially-interfering memory cells that potentially cause interference to a group of target memory cells. Partial distortion components, which are inflicted by the respective groups of the potentially-interfering memory cells on the target memory cells, are estimated. The partial distortion components are progressively accumulated so as to produce an estimated composite distortion affecting the target memory cells, while retaining only the composite distortion and not the partial distortion components. The target memory cells are read, and the interference in the target memory cells is canceled based on the estimated composite distortion.
Abstract translation: 包括以三维（3-D）配置排列的多个模拟存储器单元的存储器中的方法包括识别潜在地对一组目标存储器单元造成干扰的潜在干扰存储器单元的多个组。 估计由目标存储器单元上的潜在干扰存储器单元的相应组造成的部分失真分量。 逐渐积累部分失真分量，以产生影响目标存储器单元的估计复合失真，同时仅保留复合失真而不保留部分失真分量。 读取目标存储器单元，并且基于估计的复合失真来消除目标存储器单元中的干扰。
-
57.发明申请STORAGE IN CHARGE-TRAP MEMORY STRUCTURES USING ADDITIONAL ELECTRICALLY-CHARGED REGIONS 有权使用附加电费区的充电轨迹存储结构中的存储公开(公告)号：US20150200016A1
公开(公告)日：2015-07-16
申请号：US14457380
申请日：2014-08-12
Applicant: Apple Inc.
Inventor： Arik Rizel , Avraham Poza Meir , Yael Shur , Eyal Gurgi , Barak Baum
CPC classification number: G11C16/24 , G11C11/5671 , G11C16/0466 , G11C16/0475 , G11C16/10 , G11C16/26 , H01L27/11568 , H01L29/42328
Abstract: A device includes a memory and a read/write (R/W) unit. The memory includes multiple gates coupled to a common charge-trap layer. The R/W unit is configured to program and read the memory by creating and reading a set of electrically-charged regions in the common charge-trap layer, wherein at least a given region in the set is not uniquely associated with any single one of the gates.
Abstract translation: 一个设备包括一个存储器和一个读/写（R / W）单元。 存储器包括耦合到公共电荷陷阱层的多个门。 R / W单元被配置为通过在公共电荷陷阱层中创建和读取一组充电区域来对存储器进行编程和读取，其中集合中的至少一个给定区域不是唯一地与 大门。
-
公开(公告)号：US20150100847A1
公开(公告)日：2015-04-09
申请号：US14048492
申请日：2013-10-08
Applicant: Apple Inc.
Inventor： Shai Ojalvo , Eyal Gurgi , Yoav Kasorla
IPC: G06F11/10
CPC classification number: G06F3/0619 , G06F3/064 , G06F3/0659 , G06F3/0683 , G06F11/008 , G06F11/1012 , G06F11/1044 , G06F11/1068 , G06F11/1076 , G11C29/52
Abstract: A method includes storing data encoded with an Error Correction Code (ECC) in analog memory cells, by buffering the data in a volatile buffer and then writing the buffered data to the analog memory cells while overwriting at least some of the data in the volatile buffer with success indications. Upon detecting a failure in writing the buffered data to the analog memory cells, recovered data is produced by reading both the volatile buffer and the analog memory cells, assigning reliability metrics to respective bits of the recovered data depending on whether the bits were read from the volatile buffer or from the analog memory cells, and applying ECC decoding to the recovered data using the reliability metrics. The recovered data is re-programmed.
-
59.发明申请MITIGATING RELIABILITY DEGRADATION OF ANALOG MEMORY CELLS DURING LONG STATIC AND ERASED STATE RETENTION 有权在长期静态和擦除状态下，减轻模拟记忆细胞的可靠性降低公开(公告)号：US20140355347A1
公开(公告)日：2014-12-04
申请号：US14249448
申请日：2014-04-10
Applicant: Apple Inc.
Inventor： Yael Shur , Yoav Kasorla , Moshe Neerman , Naftali Sommer , Avraham Poza Meir , Etai Zaltsman , Eyal Gurgi , Meir Dalal
IPC: G11C16/16
CPC classification number: G11C16/14 , G11C11/5628 , G11C16/0483 , G11C16/16 , G11C16/3418 , G11C16/349
Abstract: A method in a non-volatile memory, which includes multiple memory cells that store data using a predefined set of programming levels including an erased level, includes receiving a storage operation indicating a group of the memory cells that are to be retained without programming for a long time period. The memory cells in the group are set to a retention programming level that is different from the erased level. Upon preparing to program the group of memory cells with data, the group of memory cells is erased to the erased level and the data is then programmed in the group of memory cells.
Abstract translation: 一种非易失性存储器中的方法，其包括使用包括擦除级别的预定义编程级别集存储数据的多个存储器单元，包括接收指示要保留的一组存储器单元的存储操作，而不进行编程 长时间 组中的存储单元设置为与擦除级别不同的保留编程级别。 在准备使用数据对存储器单元组进行编程时，存储器单元组被擦除到擦除的电平，然后将数据编程在存储器单元组中。
-
公开(公告)号：US20140344519A1
公开(公告)日：2014-11-20
申请号：US13897944
申请日：2013-05-20
Applicant: Apple, Inc.
Inventor： Eyal Gurgi , Micha Anholt , Yoav Kasorla
CPC classification number: G11C16/3427 , G06F3/0614 , G06F3/0653 , G06F3/0673 , G06F12/0238 , G06F12/0246 , G06F2212/1044 , G06F2212/7203 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/26 , G11C16/3418 , G11C16/3431
Abstract: A method in a memory that includes multiple analog memory cells arranged in a three-dimensional (3-D) configuration, includes identifying multiple groups of potentially-interfering memory cells that potentially cause interference to a group of target memory cells. Partial distortion components, which are inflicted by the respective groups of the potentially-interfering memory cells on the target memory cells, are estimated. The partial distortion components are progressively accumulated so as to produce an estimated composite distortion affecting the target memory cells, while retaining only the composite distortion and not the partial distortion components. The target memory cells are read, and the interference in the target memory cells is canceled based on the estimated composite distortion.
Abstract translation: 包括以三维（3-D）配置排列的多个模拟存储器单元的存储器中的方法包括识别潜在地对一组目标存储器单元造成干扰的潜在干扰存储器单元的多个组。 估计由目标存储器单元上的潜在干扰存储器单元的相应组造成的部分失真分量。 逐渐积累部分失真分量，以产生影响目标存储器单元的估计复合失真，同时仅保留复合失真而不保留部分失真分量。 读取目标存储器单元，并且基于估计的复合失真来消除目标存储器单元中的干扰。
-
-
-
-
-
-
-
-
-
Search Results
119
records
(took 0.02 seconds)
