公开(公告)号：US10545701B1

公开(公告)日：2020-01-28

申请号：US16104307

申请日：2018-08-17

Applicant: Apple Inc.

Inventor： Gregory S. Mathews ,  Kai Lun Hsiung ,  Lakshmi Narasimha Murthy Nukala ,  Peter Fu ,  Rakesh L. Notani ,  Sukalpa Biswas ,  Thejasvi Magudilu Vijayaraj ,  Yanzhe Liu ,  Shane J. Keil

IPC: G06F3/06

Abstract: Techniques relating to arbitration in a memory controller are disclosed. In some embodiments, the memory controller implements a per-bank priority-based arbitration scheme for different types of memory traffic (e.g., with different quality of service parameters). In some embodiments, the memory controller is configured to provide per-bank overrides to the arbitration scheme based on latency tolerance reported by one or more requesters sending a particular type of memory traffic. Various techniques disclosed herein may improve performance, improve fairness among different types of memory traffic, and/or reduce power consumption.

公开(公告)号：US20170277648A1

公开(公告)日：2017-09-28

申请号：US15621265

申请日：2017-06-13

Applicant: Apple Inc.

Inventor： Michael J. Smith ,  Josh P. de Cesare ,  Brijesh Tripathi ,  Derek Iwamoto ,  Shane J. Keil

IPC: G06F13/42 ,  G06F13/10 ,  G06F13/40 ,  G06F13/38

CPC classification number: G06F13/4226 ,  G06F13/105 ,  G06F13/28 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4059

Abstract: An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.

公开(公告)号：US09639143B2

公开(公告)日：2017-05-02

申请号：US14876922

申请日：2015-10-07

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Gurjeet S. Saund ,  Munetoshi Fukami ,  Shane J. Keil ,  Chaitanya Kosaraju ,  Erdem Guleyupoglu ,  Jason M. Kassoff ,  Kevin C. Wong

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  G06F1/3246 ,  G06F1/329 ,  G06F1/3293 ,  Y02D10/24 ,  Y02D50/20

Abstract: A method and apparatus for interfacing dynamic hardware power managed blocks and software power managed blocks is disclosed. In one embodiment, and integrated circuit (IC) may include a number of power manageable functional units. The functional units maybe power managed through hardware, software, or both. Each of the functional units may be coupled to at least one other functional unit through a direct communications link. A link state machine may monitor each of the communications links between functional units, and may broadcast indications of link availability to the functional units coupled to the link. Responsive to a software request to shut down a given link, or a hardware initiated shutdown of one of the functional units coupled to the link, the link state machine may broadcast and indication that the link is unavailable.

公开(公告)号：US09367081B2

公开(公告)日：2016-06-14

申请号：US14489380

申请日：2014-09-17

Applicant: Apple Inc.

Inventor： Gilbert H. Herbeck ,  Shane J. Keil

IPC: H03L7/00 ,  G06F1/12

CPC classification number: G06F1/12

Abstract: An apparatus for synchronizing two clock signals is disclosed. The apparatus may include a selection unit and circuitry. The selection unit may be configured to select a first or second clock signal as an output clock signal. A frequency of the first clock signal may be less than a frequency of the second clock signal. The circuitry may be configured to send a first signal to the selection unit, causing the selection unit to select the first clock signal. The circuitry may also be configured to send a second signal to the selection unit, causing the selection unit to select a subset of clock pulses of the second clock signal as the output clock signal. The subset of clock pulses of the second clock signal may include a clock pulse of the second clock signal corresponding to a transition of the first clock signal.

Abstract translation: 公开了一种用于同步两个时钟信号的装置。 该装置可以包括选择单元和电路。 选择单元可以被配置为选择第一或第二时钟信号作为输出时钟信号。 第一时钟信号的频率可能小于第二时钟信号的频率。 电路可以被配置为向选择单元发送第一信号，使得选择单元选择第一时钟信号。 电路还可以被配置为向选择单元发送第二信号，使得选择单元选择第二时钟信号的时钟脉冲的子集作为输出时钟信号。 第二时钟信号的时钟脉冲的子集可以包括对应于第一时钟信号的转变的第二时钟信号的时钟脉冲。

公开(公告)号：US20160077546A1

公开(公告)日：2016-03-17

申请号：US14489380

申请日：2014-09-17

Applicant: Apple Inc.

Inventor： Gilbert H. Herbeck ,  Shane J. Keil

IPC: G06F1/12

CPC classification number: G06F1/12

Abstract: An apparatus for synchronizing two clock signals is disclosed. The apparatus may include a selection unit and circuitry. The selection unit may be configured to select a first or second clock signal as an output clock signal. A frequency of the first clock signal may be less than a frequency of the second clock signal. The circuitry may be configured to send a first signal to the selection unit, causing the selection unit to select the first clock signal. The circuitry may also be configured to send a second signal to the selection unit, causing the selection unit to select a subset of clock pulses of the second clock signal as the output clock signal. The subset of clock pulses of the second clock signal may include a clock pulse of the second clock signal corresponding to a transition of the first clock signal.

Abstract translation: 公开了一种用于同步两个时钟信号的装置。 该装置可以包括选择单元和电路。 选择单元可以被配置为选择第一或第二时钟信号作为输出时钟信号。 第一时钟信号的频率可以小于第二时钟信号的频率。 电路可以被配置为向选择单元发送第一信号，使得选择单元选择第一时钟信号。 电路还可以被配置为向选择单元发送第二信号，使得选择单元选择第二时钟信号的时钟脉冲的子集作为输出时钟信号。 第二时钟信号的时钟脉冲的子集可以包括对应于第一时钟信号的转变的第二时钟信号的时钟脉冲。

公开(公告)号：US20150356050A1

公开(公告)日：2015-12-10

申请号：US14459731

申请日：2014-08-14

Applicant: Apple Inc.

Inventor： Michael J. Smith ,  Josh P. de Cesare ,  Brijesh Tripathi ,  Derek Iwamoto ,  Shane J. Keil

IPC: G06F13/42 ,  G06F13/10 ,  G06F13/40

CPC classification number: G06F13/4226 ,  G06F13/105 ,  G06F13/28 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4059

Abstract: An interface emulator for an IC is disclosed. An interface emulator includes a first first-in, first-out memory (FIFO) and a second FIFO. The first FIFO is coupled to receive data from an access port and a second FIFO coupled to receive data from at least one functional unit in the IC. The access port may be coupled to a device that is external to the IC. The external device may write information into the first FIFO, and this information may subsequently be read by a functional unit in the IC. Similarly, the functional unit may write information into the second FIFO, with the external device subsequently reading the information. Information may be written into the FIFOs in accordance with a predefined protocol. Thus, a particular type of interface may be emulated even though the physical connection and supporting circuitry for that interface is not otherwise implemented in the IC.

Abstract translation: 公开了一种用于IC的接口仿真器。 接口仿真器包括第一先入先出存储器（FIFO）和第二FIFO。 第一FIFO被耦合以从接入端口接收数据，并且第二FIFO被耦合以从IC中的至少一个功能单元接收数据。 访问端口可以耦合到IC外部的设备。 外部设备可以将信息写入第一FIFO，并且该信息随后可以由IC中的功能单元读取。 类似地，功能单元可以将信息写入第二FIFO，随后外部设备读取信息。 可以根据预定义的协议将信息写入FIFO。 因此，即使在IC中没有实现用于该接口的物理连接和支持电路，也可以模拟特定类型的接口。

公开(公告)号：US08963587B2

公开(公告)日：2015-02-24

申请号：US13893926

申请日：2013-05-14

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Raman S. Thiara ,  Shane J. Keil ,  Timothy J. Millet

IPC: H03K21/00

CPC classification number: H03K5/15013 ,  G06F1/04 ,  G06F1/08

Abstract: Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.

Abstract translation: 公开了可以允许改变耦合到集成电路内的功能块的时钟的频率的装置的实施例。 该装置可以包括多个时钟分频器和多路复用电路。 多个时钟分频器中的每一个可以将基本时钟信号的频率划分为多个除数中的相应一个。 多路复用电路可以被配置为接收多个选择信号，根据接收到的选择信号选择多个时钟分频器之一的输出，并将多个时钟分频器的选择输出耦合到功能块。

公开(公告)号：US20140340130A1

公开(公告)日：2014-11-20

申请号：US13893926

申请日：2013-05-14

Applicant: Apple Inc.

Inventor： Erik P. Machnicki ,  Raman S. Thiara ,  Shane J. Keil ,  Timothy J. Millet

IPC: H03K3/02

CPC classification number: H03K5/15013 ,  G06F1/04 ,  G06F1/08

Abstract: Embodiments of an apparatus are disclosed that may allow for changing the frequency of a clock coupled to a functional block within an integrated circuit. The apparatus may include a plurality of clock dividers and a multiplex circuit. Each of the plurality of clock dividers may divide the frequency of a base clock signal be a respective one of a plurality of divisors. The multiplex circuit may be configured to receive a plurality of selection signals, select an output from one of the plurality of clock dividers dependent upon the received selection signals, and coupled the selected output of the plurality of clock dividers to the functional block.

Abstract translation: 公开了可以允许改变耦合到集成电路内的功能块的时钟的频率的装置的实施例。 该装置可以包括多个时钟分频器和多路复用电路。 多个时钟分频器中的每一个可以将基本时钟信号的频率划分为多个除数中的相应一个。 多路复用电路可以被配置为接收多个选择信号，根据接收到的选择信号选择多个时钟分频器之一的输出，并将多个时钟分频器的选择输出耦合到功能块。

公开(公告)号：US20140167840A1

公开(公告)日：2014-06-19

申请号：US13719517

申请日：2012-12-19

Applicant: APPLE INC.

Inventor： Erik P. Machnicki ,  Gurjeet S. Saund ,  Munetoshi Fukami ,  Shane J. Keil

IPC: G05B11/01

CPC classification number: G05B11/01 ,  G06F1/3237 ,  G06F1/3253 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D50/20

Abstract: A method and apparatus for dynamic clock and power gating and decentralized wakeups is disclosed. In one embodiment, an integrated circuit (IC) includes power-manageable functional units and a power management unit. Each of the power manageable functional units is configured to convey a request to enter a low power state to the power management unit. The power management unit may respond by causing a requesting functional unit to enter the low power state. Should another functional unit initiate a request to communicate with a functional unit currently in the low power state, it may send a request to that functional unit. The receiving functional unit may respond to the request by exiting the low power state and resuming operation in the active state.

Abstract translation: 公开了一种用于动态时钟和电源门控和分散式唤醒的方法和装置。 在一个实施例中，集成电路（IC）包括功率可管理的功能单元和电源管理单元。 每个功率可管理功能单元被配置为向电力管理单元传送进入低功率状态的请求。 功率管理单元可以通过使请求功能单元进入低功率状态来进行响应。 如果另一个功能单元发起与当前处于低功率状态的功能单元通信的请求，则它可以向该功能单元发送请求。 接收功能单元可以通过退出低功率状态并在活动状态下恢复运行来响应该请求。