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公开(公告)号：US07026867B2
公开(公告)日：2006-04-11
申请号：US10879606
申请日：2004-06-28
申请人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
发明人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
IPC分类号： H03F1/02
CPC分类号： H03F3/45977 , H03F3/08
摘要： One embodiment of the present invention provides a capacitively-coupled receiver amplifier that has an input with no DC coupling. A DC voltage is programmed on the input. During programming, a transmitter is held at a voltage at a midpoint between a voltage that represents a logical “1” and a voltage that represents a logical “0” and the input voltage of the receiver amplifier is programmed to be substantially the switching-threshold voltage for the receiver amplifier. Then, during normal data communication, the transmitter drives high and low electrical signals that are coupled to the receiver amplifier. Since the input of the receiver amplifier has been substantially set to the DC voltage, the receiver amplifier need not control the DC voltage of the input for each transition in the electrical signals.
摘要翻译： 本发明的一个实施例提供一种具有不具有直流耦合的输入的电容耦合接收放大器。 在输入端编程一个直流电压。 在编程期间，发射机被保持在表示逻辑“1”的电压和表示逻辑“0”的电压之间的中点处的电压，并且接收机放大器的输入电压被编程为基本上是切换阈值 接收放大器的电压。 然后，在正常数据通信期间，发射机驱动耦合到接收放大器的高电平和低电信号。 由于接收机放大器的输入已基本设置为直流电压，所以接收放大器不需要控制电信号中每个转换的输入的直流电压。
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公开(公告)号：US06987412B2
公开(公告)日：2006-01-17
申请号：US10816761
申请日：2004-04-02
CPC分类号： H03K5/003 , H01L23/48 , H01L25/0657 , H01L2225/06527 , H01L2924/00013 , H01L2924/0002 , H03K3/037 , H03K17/689 , H01L2224/13099 , H01L2224/13599 , H01L2224/05599 , H01L2224/05099 , H01L2224/29099 , H01L2224/29599 , H01L2924/00
摘要： A system is presented for latching and amplifying a capacitively coupled inter-chip communication signal that operates by receiving an input signal on a capacitive receiver pad and feeding the input signal through an inverter to produce an output signal. The output signal is fed back through a weakened inverter to produce a feedback signal that is fed into an input of the inverter to form a latch for the input signal. The weakened inverter is biased to produce a feedback signal that swings between a high bias voltage, VH, and a low bias voltage, VL. VH is set slightly higher than the switching threshold of the inverter, and VL is set slightly lower than the switching threshold. This feedback signal causes the input signal to reside within a narrow voltage range near the switching threshold of the inverter, thereby making the inverter sensitive to small transitions in the input signal.
摘要翻译： 提出了一种用于锁存和放大电容耦合的芯片间通信信号的系统，其通过接收电容性接收器焊盘上的输入信号并通过反相器馈送输入信号以产生输出信号来操作。 输出信号通过弱化逆变器反馈，产生反馈信号，该反馈信号馈送到反相器的输入端，形成输入信号的锁存器。 弱化的逆变器被偏置以产生在高偏置电压V H H和低偏压V L之间摆动的反馈信号。 V H设定得比逆变器的切换阈值略高，并且将V L L设定得比切换阈值略低。 该反馈信号使得输入信号驻留在接近逆变器的开关阈值的窄电压范围内，从而使得反相器对输入信号中的小转变敏感。
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公开(公告)号：US06958538B1
公开(公告)日：2005-10-25
申请号：US10983250
申请日：2004-11-04
CPC分类号： G06F15/17375 , H01L2924/0002 , H01L2924/00
摘要： One embodiment of the present invention provides a proximity I/O switch, which is configured to transfer data between the components in a computer system. This proximity I/O switch is comprised of multiple switch chips, which are coupled together through capacitive coupling. This enables the multiple switch chips to communicate with each other without being constrained by the limitations of conventional non-capacitive communication mechanisms. The multiple switch chips in the proximity I/O switch are also configured to communicate with components in the computer system through conventional non-capacitive communication mechanisms.
摘要翻译： 本发明的一个实施例提供了一种接近I / O开关，其被配置为在计算机系统中的组件之间传送数据。 该接近I / O开关由多个开关芯片组成，它们通过电容耦合耦合在一起。 这使得多个开关芯片能够彼此通信，而不受传统的非电容通信机制的限制。 接近I / O开关中的多个开关芯片还被配置为通过传统的非电容通信机制与计算机系统中的组件进行通信。
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公开(公告)号：US06825708B1
公开(公告)日：2004-11-30
申请号：US10697914
申请日：2003-10-29
IPC分类号： G06G712
CPC分类号： H03K5/003 , H01L23/48 , H01L25/0657 , H01L2225/06527 , H01L2924/0002 , H01L2924/3011 , H03F1/301 , H03F1/342 , H01L2924/00
摘要： An apparatus and method for a sensing circuit for cancelling an offset voltage. Specifically, in one embodiment, a CMOS inverter amplifier amplifies an input signal present at an input node. A resistive feedback circuit is coupled to the CMOS inverter amplifier for cancelling an offset voltage that is associated with the CMOS inverter amplifier. This is accomplished by biasing the CMOS inverter amplifier to its threshold voltage. A bias circuit is coupled to the resistive feedback circuit for biasing MOSFET transistors in the resistive feedback circuit at a subthreshold conduction region. As such, the resistive feedback circuit presents a high impedance to the input node. A clamping circuit, coupled to the resistive feedback circuit, maintains operation of the transistors in the resistive feedback circuit in the subthreshold conduction region.
摘要翻译： 一种用于消除偏移电压的感测电路的装置和方法。 具体地，在一个实施例中，CMOS反相放大器放大存在于输入节点处的输入信号。 电阻反馈电路耦合到CMOS反相放大器，用于消除与CMOS反相放大器相关联的偏移电压。 这通过将CMOS反相放大器偏置到其阈值电压来实现。 偏置电路耦合到电阻反馈电路，用于在亚阈值导通区域偏置电阻反馈电路中的MOSFET晶体管。 因此，电阻反馈电路对输入节点呈现高阻抗。 耦合到电阻反馈电路的钳位电路在亚阈值导通区域中保持电阻反馈电路中的晶体管的操作。
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公开(公告)号：US06696876B2
公开(公告)日：2004-02-24
申请号：US09759981
申请日：2001-01-12
申请人： Robert J. Drost , Robert J. Bosnyak
发明人： Robert J. Drost , Robert J. Bosnyak
IPC分类号： H03K300
摘要： A clock interpolation circuit for setting and controlling a phase of an output clock that is derived from an interpolation of multiple input clocks. Interpolation is performed by capacitively weighting the multiple clocks. A select and control circuit provides the ability to select different capacitance values to control the weighting. An optional buffer stage is also provided to sharpen the edge transitions of the interpolated clock.
摘要翻译： 一种用于设置和控制从多个输入时钟的内插导出的输出时钟的相位的时钟插值电路。 通过对多个时钟进行电容加权来执行插值。 选择和控制电路提供选择不同电容值以控制加权的能力。 还提供了可选的缓冲级，以锐化内插时钟的边沿转换。
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56.发明授权Selectable resistor and/or driver for an integrated circuit with a linear resistance 有权具有线性电阻的集成电路的可选电阻和/或驱动器公开(公告)号：US06509765B1
公开(公告)日：2003-01-21
申请号：US09990729
申请日：2001-11-20
申请人： Robert J. Drost
发明人： Robert J. Drost
IPC分类号： H03K300
CPC分类号： H04L25/0278 , H03K19/00384 , H04L25/028
摘要： One embodiment of the present invention provides resistor within an integrated circuit with a substantially linear resistance. This resistor includes a diode-connected transistor coupled in parallel with a current-source-connected transistor, so that a nonlinear resistance of the diode-connected transistor combines with a nonlinear resistance of the current-source-connected transistor to produce a substantially linear combined resistance. It also includes selection circuit that is configured to selectively deactivate the resistor by deactivating the diode-connected transistor and the current-source-connected transistor. This selection circuit provides a range of possible resistance values, and thus enables the resistance to be quickly switched on and off to allow for use in a high-speed driver circuit.
摘要翻译： 本发明的一个实施例提供具有基本线性电阻的集成电路内的电阻器。 该电阻器包括与电流源连接的晶体管并联耦合的二极管连接的晶体管，使得二极管连接的晶体管的非线性电阻与电流源连接的晶体管的非线性电阻相结合，以产生基本上线性的组合 抵抗性。 它还包括选择电路，其被配置为通过去激活二极管连接的晶体管和电流源连接的晶体管来选择性地去激活电阻。 该选择电路提供可能的电阻值的范围，因此能够快速地打开和关闭电阻以允许在高速驱动电路中使用。
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57.发明授权Method and apparatus that models neural transmission to amplify a capacitively-coupled input signal 有权模拟神经传输以放大电容耦合输入信号的方法和装置公开(公告)号：US06472931B1
公开(公告)日：2002-10-29
申请号：US09991475
申请日：2001-11-16
IPC分类号： G06G712
CPC分类号： H03K17/167 , H03K3/356104
摘要： One embodiment of the present invention provides a system for amplifying an input signal received from a capacitive sensor. The system includes an input for receiving an input signal from the capacitive sensor and an amplifier that amplifies the input signal to produce an output signal. This amplifier includes a pull-up circuit that pulls the output signal up to a high voltage when the input signal exceeds a threshold voltage. It also includes a pull-down circuit that pulls the output signal down to a low voltage when the input signal falls below the threshold voltage. After the output signal is pulled up to the high voltage, the pull-up circuit enters a refractory state in which the pull-up circuit uses a limited current, and the pull-down circuit enters a receptive state in which the pull-down circuit is sensitized to react to small changes in the input signal. After the output signal is pulled down to the low voltage, the pull-down circuit enters a refractory state in which the pull-down circuit uses a limited current, and the pull-up circuit enters a receptive state in which the pull-up circuit is sensitized to react to small changes in the input signal.
摘要翻译： 本发明的一个实施例提供一种用于放大从电容式传感器接收的输入信号的系统。 该系统包括用于接收来自电容传感器的输入信号的输入端和放大输入信号以产生输出信号的放大器。 该放大器包括上拉电路，当输入信号超过阈值电压时，该上拉电路将输出信号拉高至高电压。 它还包括一个下拉电路，当输入信号低于阈值电压时，它将输出信号拉低至低电压。 在将输出信号上拉至高电压之后，上拉电路进入上拉电路使用有限电流的难处理状态，并且下拉电路进入接收状态，其中下拉电路 对输入信号的小变化敏感。 在输出信号被拉低至低电压之后，下拉电路进入下拉电路使用有限电流的难处理状态，并且上拉电路进入接收状态，其中上拉电路 对输入信号的小变化敏感。
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58.发明授权
公开(公告)号：US06148038A
公开(公告)日：2000-11-14
申请号：US828506
申请日：1997-03-31
申请人： Robert J. Drost , Robert J. Bosnyak
发明人： Robert J. Drost , Robert J. Bosnyak
CPC分类号： H04L25/4904 , H03H5/12
摘要： A decoder circuit for decoding phase-encoded digital data signals includes a timing circuit and a signal viewer circuit coupled to logic circuitry. The timing circuit uses an edge of a received phase-encoded digital data signal to indicate when to sample data from the received phase-encoded digital data signal in the signal viewer circuit. The logic circuitry determines the value encoded in the phase-encoded digital data signal based on the sampled data.
摘要翻译： 用于解码相位编码的数字数据信号的解码器电路包括定时电路和耦合到逻辑电路的信号查看器电路。 定时电路使用接收的相位编码数字数据信号的边沿来指示何时在信号查看器电路中从接收到的相位编码的数字数据信号中采样数据。 逻辑电路基于采样数据确定编码在相位编码数字数据信号中的值。
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59.发明授权Phase error cancellation method and apparatus for high performance data recovery 失效用于高性能数据恢复的相位误差消除方法和装置
公开(公告)号：US5963606A
公开(公告)日：1999-10-05
申请号：US884052
申请日：1997-06-27
申请人： Robert J. Drost , Robert J. Bosnyak
发明人： Robert J. Drost , Robert J. Bosnyak
CPC分类号： H03L7/0805 , H03L7/07 , H03L7/0812 , H03L7/0995 , H04L7/0037 , H04L7/0337 , H04L7/0041
摘要： A phase error cancellation apparatus captures data bits of a serialized data stream with reduced phase error by aligning a generated clock signal to the data stream. The phase error cancellation apparatus includes a data delay pipe, a clock generator, a clock delay pipe, and a data stream sampling element. The data delay pipe receives the data stream and delays the data bits by a first amount. The clock generator generates a clock signal that the clock delay pipe delays by a second amount. The data stream sampling element receives the delayed data bits and the delayed clock signal, and samples the delayed data bits using the delayed clock signal to recover the data bits from the data stream with reduced phase error.
摘要翻译： 相位误差消除装置通过将生成的时钟信号与数据流对齐来捕获具有减小的相位误差的串行化数据流的数据位。 相位误差消除装置包括数据延迟管，时钟发生器，时钟延迟管和数据流采样元件。 数据延迟管接收数据流并将数据位延迟第一个量。 时钟发生器产生时钟延迟管延迟第二个量的时钟信号。 数据流采样单元接收延迟的数据位和延迟的时钟信号，并使用延迟的时钟信号对延迟的数据位进行采样，以从相位误差减小的数据流中恢复数据位。
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公开(公告)号：US5485106A
公开(公告)日：1996-01-16
申请号：US222988
申请日：1994-04-05
IPC分类号： H03K3/021 , H03K17/567 , H03K19/0175 , H03K19/082 , H03K19/0948
CPC分类号： H03K17/567 , H03K19/017563 , H03K3/021
摘要： An efficient high-speed ECL to CMOS logic converter for BiCMOS integrated circuits. In one embodiment, a differential amplifier compares an ECL input signal to an ECL reference voltage and generates a pair of complementary intermediate signals on a corresponding pair of differential output nodes. The differential amplifier has two load resistors coupled in series with a common load resistor which limits the upper voltage swing at the differential output nodes. A regenerative stage coupled to the differential output nodes switches between a partially on state and a fully on state in response to the complementary intermediate signals. A pair of inverter stages convert the complementary intermediate signals into a pair of CMOS level signals. A pair of complementary output drivers coupled to the respective complementary inverter stages provide current driving capability. In this embodiment, each output driver includes a CMOS inverter pair and a bipolar transistor coupled between the respective output node of the driver and V.sub.DD.
摘要翻译： 用于BiCMOS集成电路的高效ECL至CMOS逻辑转换器。 在一个实施例中，差分放大器将ECL输入信号与ECL参考电压进行比较，并在对应的差分输出节点对上生成一对互补中间信号。 差分放大器具有与公共负载电阻串联耦合的两个负载电阻，其限制差分输出节点处的高电压摆幅。 耦合到差分输出节点的再生级响应于互补的中间信号在部分导通状态和完全导通状态之间切换。 一对反相器级将互补的中间信号转换为一对CMOS电平信号。 耦合到相应的互补反相器级的一对互补输出驱动器提供电流驱动能力。 在本实施例中，每个输出驱动器包括耦合在驱动器的相应输出节点与VDD之间的CMOS反相器对和双极晶体管。
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