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151 条记录 (耗时 0.022 秒)

    Photodiode structure augmented with active area photosensitive regions
    52.
    发明授权
    Photodiode structure augmented with active area photosensitive regions 失效
    光电二极管结构增加了有源区光敏区

    公开(公告)号：US5982011A

    公开(公告)日：1999-11-09

    申请号：US977468

    申请日：1997-11-24

    申请人： Alexander Kalnitsky ,  Marco Sabatini

    发明人： Alexander Kalnitsky ,  Marco Sabatini

    IPC分类号： H01L27/144 ,  H01L27/14

    CPC分类号： H01L27/144

    摘要： A photodiode structure augmented with active area photosensitive regions is used for detecting impinging radiation. The photodiode includes a semiconductor base layer doped with impurities of a first carrier type, a field oxide layer disposed upon the base layer with an opening formed therethrough, a plurality of auxiliary oxide layers wherein each is separately disposed upon the base layer, and a semiconductor diffusion layer doped with impurities of a second carrier type arranged upon the base layer and in contact with the oxide layers. When the photodiode is electrically energized, a plurality of integral photosensitive regions is created within the depletion region to facilitate the detection of impinging radiation at an increased quantum efficiency.

    摘要翻译： 增加了有源区光敏区域的光电二极管结构用于检测入射辐射。 光电二极管包括掺杂有第一载流子类型的杂质的半导体基底层，设置在其上形成有开口的基底层上的场氧化物层，其中分别设置在基底层上的多个辅助氧化物层，以及半导体 扩散层，掺杂有布置在基底层上并与氧化物层接触的第二载体类型的杂质。 当光电二极管被通电时，在耗尽区内产生多个整体感光区域，以便以增加的量子效率检测入射辐射。

    Method of forming a polysilicon buried contact
    53.
    发明授权
    Method of forming a polysilicon buried contact 失效
    形成多晶硅掩埋触点的方法

    公开(公告)号：US5589418A

    公开(公告)日：1996-12-31

    申请号：US342863

    申请日：1994-11-21

    申请人： Alexander Kalnitsky

    发明人： Alexander Kalnitsky

    IPC分类号： H01L21/74 ,  H01L21/44

    CPC分类号： H01L21/743 ,  Y10S438/97

    摘要： A method is provided for forming a polysilicon buried contact of an integrated circuit, and an integrated circuit formed according to the same. A field oxide region is formed over a portion of a substrate leaving an exposed active region. An oxide layer is formed over the active region. A first photoresist layer is formed and patterned over the first silicon layer. The first silicon layer is then etched to form an opening therethrough to expose a portion of the oxide layer. The oxide layer is etched through the opening to expose a portion of the substrate. A conductive etch stop layer is formed over the exposed portion of the substrate and the first photoresist layer. The first photoresist layer and the etch stop layer overlying the first photoresist layer are then removed. A second silicon layer is formed over the first silicon layer and the remaining etch stop layer. A second photoresist layer is formed and patterned over the second silicon layer. The first and second silicon layers are then etched to form a conductive structure contacting the exposed portion of the substrate through the etch stop layer.

    摘要翻译： 提供一种用于形成集成电路的多晶硅埋入触点的方法和根据该集成电路形成的集成电路。 在衬底的一部分上形成场氧化物区域，留下暴露的有源区。 在有源区上形成氧化物层。 在第一硅层上形成并图案化第一光致抗蚀剂层。 然后蚀刻第一硅层以形成其中的开口以暴露氧化物层的一部分。 通过开口蚀刻氧化物层以暴露基板的一部分。 在衬底和第一光致抗蚀剂层的暴露部分上形成导电蚀刻停止层。 然后去除覆盖在第一光致抗蚀剂层上的第一光致抗蚀剂层和蚀刻停止层。 在第一硅层和剩余的蚀刻停止层上形成第二硅层。 在第二硅层上形成并图案化第二光致抗蚀剂层。 然后蚀刻第一和第二硅层以形成通过蚀刻停止层接触衬底的暴露部分的导电结构。

    Structure and method for a switched circuit device
    55.
    发明授权
    Structure and method for a switched circuit device 有权
    一种开关电路器件的结构和方法

    公开(公告)号：US09209683B2

    公开(公告)日：2015-12-08

    申请号：US13599909

    申请日：2012-08-30

    申请人： Alexander Kalnitsky

    发明人： Alexander Kalnitsky

    IPC分类号： G05F1/46 ,  H02M3/155 ,  H01L29/78

    CPC分类号： H02M3/155 ,  H01L29/78 ,  H01L29/7816

    摘要： The present disclosure provides a switched voltage converter for receiving a source voltage and producing an output voltage. The voltage converter comprises a switch controller and a switched device communicatively coupled to the switch controller. The switch controller adjusts the output voltage by controlling a duty cycle of the switched device. The switched device is sized such that it is characterized by a drain-to-source breakdown voltage greater than or substantially equal to the source voltage and the output voltage and is further characterized by a hot-carrier injection rating less than the source voltage or the output voltage. In further embodiments, the switched device is sized such that it is characterized by a drain-to-source breakdown voltage greater than or substantially equal to a peak operating voltage and is further characterized by a hot-carrier injection rating less than the peak operating voltage.

    摘要翻译： 本公开提供了一种用于接收源极电压并产生输出电压的开关电压转换器。 电压转换器包括开关控制器和通信地耦合到开关控制器的开关装置。 开关控制器通过控制开关器件的占空比来调节输出电压。 开关器件的尺寸使得其特征在于漏极 - 源极击穿电压大于或基本上等于源极电压和输出电压，并且进一步的特征在于热载流子注入额定值小于源极电压或 输出电压。 在另外的实施例中，开关器件的尺寸使得其特征在于漏极 - 源极击穿电压大于或基本上等于峰值工作电压，并且进一步的特征在于小于峰值工作电压的热载流子注入额定值 。

    Silicon wafer strength enhancement
    56.
    发明授权
    Silicon wafer strength enhancement 有权
    硅片强度提高

    公开(公告)号：US09123671B2

    公开(公告)日：2015-09-01

    申请号：US12982275

    申请日：2010-12-30

    申请人： Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang ,  Alexander Kalnitsky

    发明人： Chi-Ming Chen ,  Chung-Yi Yu ,  Chia-Shiung Tsai ,  Ho-Yung David Hwang ,  Alexander Kalnitsky

    IPC分类号： H01L21/322

    CPC分类号： H01L21/3225

    摘要： Provided is a method of fabricating a semiconductor device. The method includes: receiving a silicon wafer that contains oxygen; forming a zone in the silicon wafer, the zone being substantially depleted of oxygen; causing a nucleation process to take place in the silicon wafer to form oxygen nuclei in a region of the silicon wafer outside the zone; and growing the oxygen nuclei into defects. Also provided is an apparatus that includes a silicon wafer. The silicon wafer includes: a first portion that is substantially free of oxygen, the first portion being disposed near a surface of the silicon wafer; and a second portion that contains oxygen; wherein the second portion is at least partially surrounded by the first portion.

    摘要翻译： 提供一种制造半导体器件的方法。 该方法包括：接收含有氧的硅晶片; 在硅晶片中形成区域，该区域基本上耗尽氧气; 导致在硅晶片中发生成核过程，以在区域外的硅晶片的区域中形成氧核; 并将氧原子生长成缺陷。 还提供了一种包括硅晶片的装置。 硅晶片包括：基本上不含氧的第一部分，第一部分设置在硅晶片的表面附近; 和含有氧的第二部分; 其中所述第二部分至少部分地被所述第一部分包围。

    MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS
    59.
    发明申请
    MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS 有权
    基于盖帽的不挥发性记忆细胞的记忆阵列

    公开(公告)号：US20110116324A1

    公开(公告)日：2011-05-19

    申请号：US13012368

    申请日：2011-01-24

    申请人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Michael D. Church ,  Yun Yue

    发明人： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Michael D. Church ,  Yun Yue

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0433

    摘要： A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.

    摘要翻译： 存储器阵列包括以行和列的矩阵组织的多个存储器单元。 每个存储单元包括高电压存取晶体管，电连接到存取晶体管的浮动栅极存储晶体管和电连接到存储晶体管的耦合电容器。 第一组字线分别电连接到相应行中的每个存储器单元中的电容器。 第二组字线各自电连接到相应行中的每个存储单元中的存取晶体管。 第一组位线分别电连接到相应列中每个存储单元中的存取晶体管。 第二组位线分别电连接到相应列中每个存储器单元中的存储晶体管。 在操作中可以对字线和位线施加电压的各种组合，以对存储器晶体管存储在一个或多个存储器单元中的逻辑状态进行编程，擦除，读取或禁止。

    Method and apparatus for shielding tunneling circuit and floating gate for integration of a floating gate voltage reference in a general purpose CMOS technology
    60.
    发明授权
    Method and apparatus for shielding tunneling circuit and floating gate for integration of a floating gate voltage reference in a general purpose CMOS technology 失效
    用于屏蔽隧道电路和浮栅的方法和装置，用于在通用CMOS技术中集成浮栅参考电压

    公开(公告)号：US07759727B2

    公开(公告)日：2010-07-20

    申请号：US11639658

    申请日：2006-12-14

    申请人： Alexander Kalnitsky ,  John M. Caruso

    发明人： Alexander Kalnitsky ,  John M. Caruso

    IPC分类号： G11C16/04

    CPC分类号： G11C27/005 ,  G11C16/3418 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11558 ,  H01L29/7883

    摘要： A method and corresponding structure for shielding a floating gate tunneling element. The method comprises disposing a floating gate over a gate oxide using standard CMOS processing in two active areas defined by first and second doped well regions formed in a substrate surrounded by field oxide, and forming a floating gate shield layer so as to enclose the floating gate. The floating gate includes a first floating gate portion over an active area in the first doped well region and a second floating gate portion over the active area in the second doped well region. The first floating gate portion is substantially smaller than the second floating gate portion so as to enable adequate voltage coupling for Fowler-Nordheim tunneling to occur between the first doped well region and the first floating gate portion. The direction of tunneling is determined by high voltage application to one of the doped well regions.

    摘要翻译： 一种用于屏蔽浮动栅极隧道元件的方法和相应的结构。 该方法包括使用在由场氧化物包围的衬底中形成的第一和第二掺杂阱区域限定的两个有源区域中的标准CMOS处理在栅极氧化物上设置浮置栅极，以及形成浮置栅极屏蔽层以便包围浮置栅极 。 浮置栅极包括在第一掺杂阱区域中的有源区域上的第一浮动栅极部分和位于第二掺杂阱区域中的有源区域上的第二浮动栅极部分。 第一浮栅部分基本上小于第二浮栅部分，以便能够在第一掺杂阱区域和第一浮栅部分之间产生用于Fowler-Nordheim隧道的足够的电压耦合。 通过高压施加到掺杂阱区之一来确定隧道的方向。