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    Photodiode structure augmented with active area photosensitive regions
    1.
    发明授权
    Photodiode structure augmented with active area photosensitive regions 失效
    光电二极管结构增加了有源区光敏区

    公开(公告)号：US5982011A

    公开(公告)日：1999-11-09

    申请号：US977468

    申请日：1997-11-24

    Applicant: Alexander Kalnitsky ,  Marco Sabatini

    Inventor： Alexander Kalnitsky ,  Marco Sabatini

    IPC: H01L27/144 ,  H01L27/14

    CPC classification number: H01L27/144

    Abstract: A photodiode structure augmented with active area photosensitive regions is used for detecting impinging radiation. The photodiode includes a semiconductor base layer doped with impurities of a first carrier type, a field oxide layer disposed upon the base layer with an opening formed therethrough, a plurality of auxiliary oxide layers wherein each is separately disposed upon the base layer, and a semiconductor diffusion layer doped with impurities of a second carrier type arranged upon the base layer and in contact with the oxide layers. When the photodiode is electrically energized, a plurality of integral photosensitive regions is created within the depletion region to facilitate the detection of impinging radiation at an increased quantum efficiency.

    Abstract translation: 增加了有源区光敏区域的光电二极管结构用于检测入射辐射。 光电二极管包括掺杂有第一载流子类型的杂质的半导体基底层，设置在其上形成有开口的基底层上的场氧化物层，其中分别设置在基底层上的多个辅助氧化物层，以及半导体 扩散层，掺杂有布置在基底层上并与氧化物层接触的第二载体类型的杂质。 当光电二极管被通电时，在耗尽区内产生多个整体感光区域，以便以增加的量子效率检测入射辐射。

    Solid state optical imaging pixel with resistive load
    3.
    发明授权
    Solid state optical imaging pixel with resistive load 失效
    具有电阻负载的固态光学成像像素

    公开(公告)号：US06188056B1

    公开(公告)日：2001-02-13

    申请号：US09103753

    申请日：1998-06-24

    Applicant: Alexander Kalnitsky ,  Frank Randolph Bryant ,  Marco Sabatini

    Inventor： Alexander Kalnitsky ,  Frank Randolph Bryant ,  Marco Sabatini

    IPC: H01L2700

    CPC classification number: H01L27/14665 ,  H01L27/14609 ,  H01L31/0352

    Abstract: Disclosed is a CMOS image sensor that includes pixels employing a radiation-sensitive resistive element in which the resistance of the element changes in response to the quantity of radiation striking it. The resistive elements are made from an appropriately doped polycrystalline semiconductor material such as polysilicon. The pixels are provided on a semiconductor device in which the photosensitive resistive elements are provided on a first layer and the pixel associated transistors are provided on a second layer. The fill factor may be approach 100 percent for such pixels.

    Abstract translation: 公开了一种CMOS图像传感器，其包括采用辐射敏感电阻元件的像素，其中元件的电阻响应于其的辐射量而变化。 电阻元件由诸如多晶硅的适当掺杂的多晶半导体材料制成。 像素设置在半导体器件上，其中光敏电阻元件设置在第一层上，像素相关联的晶体管设置在第二层上。 这种像素的填充因子可能接近100％。

    Method of manufacturing junction barrier schottky diode with dual silicides
    5.
    发明授权
    Method of manufacturing junction barrier schottky diode with dual silicides 有权
    制造具有双重硅化物的结型肖特基二极管的方法

    公开(公告)号：US08647971B2

    公开(公告)日：2014-02-11

    申请号：US13356624

    申请日：2012-01-23

    Applicant: Dev Alok Girdhar ,  Michael David Church ,  Alexander Kalnitsky

    Inventor： Dev Alok Girdhar ,  Michael David Church ,  Alexander Kalnitsky

    IPC: H01L21/28 ,  H01L21/44

    CPC classification number: H01L29/872 ,  H01L27/0629 ,  H01L29/456 ,  H01L29/47 ,  H01L29/7833

    Abstract: An integrated circuit, including a junction barrier Schottky diode, has an N type well, a P-type anode region in the surface of the well, and an N-type Schottky region in the surface of the well and horizontally abutting the anode region. A first silicide layer is on and makes a Schottky contact to the Schottky region and is on an adjoining anode region. A second silicide layer of a different material than the first silicide is on the anode region. An ohmic contact is made to the second silicide on the anode region and to the well.

    Abstract translation: 包括结势垒肖特基二极管的集成电路具有N型阱，阱表面中的P型阳极区域和阱表面中的N型肖特基区域，并且水平地邻接阳极区域。 第一硅化物层在肖特基区域上并与其相邻的阳极区域形成肖特基接触。 与第一硅化物不同的第二硅化物层位于阳极区上。 对阳极区域和阱的第二硅化物进行欧姆接触。

    Light sensors with infrared suppression
    6.
    发明授权
    Light sensors with infrared suppression 有权
    红外线抑制光传感器

    公开(公告)号：US07960766B2

    公开(公告)日：2011-06-14

    申请号：US12817101

    申请日：2010-06-16

    Applicant: Alexander Kalnitsky ,  Dong Zheng ,  Joy Jones ,  Xijian Lin ,  Gregory Cestra

    Inventor： Alexander Kalnitsky ,  Dong Zheng ,  Joy Jones ,  Xijian Lin ,  Gregory Cestra

    IPC: H01L31/062

    CPC classification number: H01L31/103 ,  H01L27/1443 ,  H01L31/02162

    Abstract: Embodiments of the present invention are directed to light sensors, that primarily respond to visible light while suppressing infrared light. Such sensors are especially useful as ambient light sensors because such sensors can be used to provide a spectral response similar to that of a human eye. Embodiments of the present invention are also directed to methods of providing such light sensors, and methods for using such light sensors.

    Abstract translation: 本发明的实施例涉及在抑制红外光的同时主要响应于可见光的光传感器。 这种传感器作为环境光传感器是特别有用的，因为这样的传感器可用于提供类似于人眼的光谱响应。 本发明的实施例还涉及提供这种光传感器的方法，以及使用这种光传感器的方法。

    MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS
    7.
    发明申请
    MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS 有权

    公开(公告)号：US20110116319A1

    公开(公告)日：2011-05-19

    申请号：US13012381

    申请日：2011-01-24

    Applicant: Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Michael D. Church ,  Yun Yue

    Inventor： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Michael D. Church ,  Yun Yue

    IPC: G11C16/26

    CPC classification number: G11C16/0433

    Abstract: A memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a high voltage access transistor, a floating gate memory transistor electrically connected to the access transistor, and a coupling capacitor electrically connected to the memory transistor. A first set of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A second set of word lines are each electrically connected to the access transistor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the access transistor in each of the memory cells in a respective column. A second set of bit lines are each electrically connected to the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and bit lines in operations to program, erase, read, or inhibit a logic state stored by the memory transistor in one or more of the memory cells.

    FLASH MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS
    8.
    发明申请
    FLASH MEMORY ARRAY OF FLOATING GATE-BASED NON-VOLATILE MEMORY CELLS 有权
    基于盖板的非易失性记忆体的闪存存储阵列

    公开(公告)号：US20100149879A1

    公开(公告)日：2010-06-17

    申请号：US12711520

    申请日：2010-02-24

    Applicant: Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Prabhjot Singh ,  Michael D. Church

    Inventor： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Prabhjot Singh ,  Michael D. Church

    IPC: G11C16/04

    CPC classification number: G11C16/0416

    Abstract: A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.

    Abstract translation: 闪存阵列包括以行和列的矩阵组织的多个存储单元。 每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。 多个字线各自电连接到相应行中的每个存储器单元中的电容器。 第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。 多个高压存取晶体管分别电连接到第一组位线中的位线。 第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。 在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。

    Flash memory array of floating gate-based non-volatile memory cells
    9.
    发明授权
    Flash memory array of floating gate-based non-volatile memory cells 有权
    基于浮动栅极的非易失性存储单元的闪存阵列

    公开(公告)号：US07688627B2

    公开(公告)日：2010-03-30

    申请号：US11861102

    申请日：2007-09-25

    Applicant: Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Prabhjot Singh ,  Michael D. Church

    Inventor： Hosam Haggag ,  Alexander Kalnitsky ,  Edgardo Laber ,  Prabhjot Singh ,  Michael D. Church

    IPC: G11C14/00 ,  G11C16/04

    CPC classification number: G11C16/0416

    Abstract: A flash memory array comprises a plurality of memory cells organized in a matrix of rows and columns. Each of the memory cells includes a floating gate memory transistor having a source region and a drain region, and a coupling capacitor electrically connected to the memory transistor. A plurality of word lines are each electrically connected to the capacitor in each of the memory cells in a respective row. A first set of bit lines are each electrically connected to the drain region of the memory transistor in each of the memory cells in a respective column. A plurality of high voltage access transistors are each electrically connected to a bit line in the first set of bit lines. A second set of bit lines are each electrically connected to the source region of the memory transistor in each of the memory cells in a respective column. Various combinations of voltages can be applied to the word lines and the first and second sets of bit lines in operations to erase, program, inhibit, or read the logic state stored by the memory transistor in one or more of the memory cells.

    Abstract translation: 闪存阵列包括以行和列的矩阵组织的多个存储单元。 每个存储单元包括具有源极区和漏极区的浮动栅极存储晶体管，以及电连接到存储晶体管的耦合电容。 多个字线各自电连接到相应行中的每个存储器单元中的电容器。 第一组位线分别电连接到相应列中的每个存储单元中的存储晶体管的漏极区。 多个高压存取晶体管分别电连接到第一组位线中的位线。 第二组位线分别电连接到相应列中的每个存储器单元中的存储晶体管的源极区域。 在操作中可以对字线和第一和第二组位线施加电压的各种组合，以擦除，编程，禁止或读取存储器晶体管存储在一个或多个存储器单元中的逻辑状态。

    PHOTODIODE FOR MULTIPLE WAVELENGTH OPERATION
    10.
    发明申请
    PHOTODIODE FOR MULTIPLE WAVELENGTH OPERATION 失效
    多波长光圈操作

    公开(公告)号：US20090174021A1

    公开(公告)日：2009-07-09

    申请号：US12365141

    申请日：2009-02-03

    Applicant: Dong Zheng ,  Phillip J. Benzel ,  Joy Jones ,  Alexander Kalnitsky ,  Perumal Ratnam

    Inventor： Dong Zheng ,  Phillip J. Benzel ,  Joy Jones ,  Alexander Kalnitsky ,  Perumal Ratnam

    IPC: H01L31/0232

    CPC classification number: H01L27/1462 ,  H01L27/1463 ,  H01L31/02165

    Abstract: A photodiode includes a substrate having a first semiconductor type surface region on at least a portion thereof, and a second semiconductor type surface layer formed in a portion of the surface region. A multi-layer anti-reflective coating (ARC) is on the second semiconductor type surface layer, wherein the multi-layer ARC comprises at least two different dielectric layers. A layer resistant to oxide etch is above a peripheral portion the multi-layer ARC. Further layers are above the layer resistant to oxide etch, and thereby above the peripheral portion the multi-layer ARC. A window extends down to the multi-layer ARC. A photodiode region is formed by a pn-junction of the first semiconductor type surface region and the second semiconductor type surface layer.

    Abstract translation: 光电二极管包括在其至少一部分上具有第一半导体型表面区域的基板和形成在表面区域的一部分中的第二半导体型表面层。 多层抗反射涂层（ARC）在第二半导体型表面层上，其中多层ARC包括至少两个不同的电介质层。 耐氧化物蚀刻的层在多层ARC的外围部分之上。 另外的层在耐氧化物蚀刻层上方，并且因此在多层ARC的周边部分之上。 一个窗口向下延伸到多层ARC。 光电二极管区域由第一半导体型表面区域和第二半导体型表面层的pn结形成。

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