公开(公告)号：US12197938B1

公开(公告)日：2025-01-14

申请号：US17643756

申请日：2021-12-10

Applicant: Amazon Technologies, Inc.

Inventor： Ali Ghassan Saidi ,  Adi Habusha

IPC: G06F9/455 ,  G06F13/16 ,  G06F13/42

Abstract: An input/output (I/O) device can initiate data migration of a virtual machine (VM) instance from a source device to a target device. The data migration of the VM instance may include migrating the data for the VM instance and tag data associated with the data. The data for the VM instance and the tag data may be stored together in a source memory. A first read request from the I/O device can enable a memory controller in the source device to read the data for the VM instance and the tag data together, store the tag data in a tag data buffer, and transmit the data for the VM instance to the target device. A second read request from the I/O device can read the stored tag data from the tag data buffer and transmit to the target device. The target device can write the data for the VM instance together with the tag data in the target memory.

公开(公告)号：US12093189B1

公开(公告)日：2024-09-17

申请号：US16588394

申请日：2019-09-30

Applicant: Amazon Technologies, Inc.

Inventor： Ali Ghassan Saidi ,  Adi Habusha ,  Roland Paterson-Jones ,  Ohad Gdalyahu

IPC: G06F12/122

CPC classification number: G06F12/122 ,  G06F2212/1016 ,  G06F2212/304

Abstract: Methods and integrated circuit devices for recording memory-side page activity are provided. Memory systems typically have a combination of faster memory devices and slower memory devices. Frequently accessed memory pages (hot pages) should be maintained in the faster memory devices while less frequently accessed memory pages (cold pages) should be maintained in the slower memory devices. To determine the memory pages that should be moved between the faster memory devices and the slower memory devices, counters may be implemented to count transactions to the memory pages. The counter values may be periodically checked to identify memory pages that can be moved from faster memory devices to slower memory devices, and vice-versa.

公开(公告)号：US11880327B1

公开(公告)日：2024-01-23

申请号：US17643132

申请日：2021-12-07

Applicant: Amazon Technologies, Inc.

Inventor： Guy Nakibly ,  Barak Wasserstrom ,  Yaniv Shapira ,  Erez Izenberg ,  Adi Habusha

IPC: G06F13/40

CPC classification number: G06F13/4027

Abstract: A coherent connection and a non-coherent connection are provided between system-on-chips (SoCs). The coherent connection can be coupled to coherent interconnects on the SoCs, and the non-coherent connection can be coupled to non-coherent interconnects on the SoCs. An input/output (I/O) transaction from an I/O device on a first SoC that is targeted to a second SoC can be transmitted via the non-coherent connection, and a processor transaction from the first SoC that is targeted to the second SoC can be transmitted via the coherent connection.

公开(公告)号：US20220253392A1

公开(公告)日：2022-08-11

申请号：US17660797

申请日：2022-04-26

Applicant: Amazon Technologies, Inc.

Inventor： Nafea Bshara ,  Adi Habusha ,  Guy Nakibly ,  Georgy Machulsky

IPC: G06F13/10 ,  G06F13/24 ,  G06F13/42 ,  G06F9/50

Abstract: Techniques for emulating a configuration space may include emulating a set of configuration registers for a set of functions corresponding to a type of peripheral device. The set of functions can include a physical function and a virtual function associated with the physical function. A configuration access request can be processed by retrieving an emulated configuration register from the emulated configuration space, and logging incoming configuration access requests in a configuration transaction log to track configuration accesses.

公开(公告)号：US11182103B1

公开(公告)日：2021-11-23

申请号：US16261198

申请日：2019-01-29

Applicant: Amazon Technologies, Inc.

Inventor： Itai Avron ,  Adi Habusha ,  Uri Leder ,  Svetlana Kantorovych

IPC: G06F3/06 ,  G06F12/0806 ,  G06F12/0875 ,  G06F12/0873

Abstract: A dedicated input/output (I/O) cache can be used for I/O-to-processor communications. Data received from an I/O device can be written to the I/O cache and also written to a device memory that is accessible to the processor. The processor can then access the data in the fast, dedicated I/O cache if available. Otherwise, the processor can read the data from the memory into a conventional processor cache for processing. Writes to the cache can be full or partial, with partial writes utilizing padding in some embodiments. The data can be written sequentially in a circular manner. Data processed by the processor can be invalidated, and invalidated data can be overwritten on a subsequent write. Phase bits can also be used to indicate the pass during which various writes were performed.

公开(公告)号：US11126474B1

公开(公告)日：2021-09-21

申请号：US15622490

申请日：2017-06-14

Applicant: Amazon Technologies, Inc.

Inventor： Tzachi Zidenberg ,  Adi Habusha ,  Zeev Zilberman

IPC: G06F9/52 ,  G06F9/455 ,  G06F9/48 ,  G06F9/50

Abstract: Techniques for reducing the probability of spinlock and/or reducing the time that a virtual central processing unit (CPU) may hold a lock are provided. In one embodiment, a computer-implemented method includes determining that an executing virtual CPU is holding a lock for exclusive use of a resource, and scheduling the executing virtual CPU to run for up to a specified time period before de-scheduling the executing virtual CPU. In one embodiment, the executing virtual CPU holding the lock writes a value to a register to indicate that the executing virtual CPU is holding the lock.

公开(公告)号：US11042494B1

公开(公告)日：2021-06-22

申请号：US16014833

申请日：2018-06-21

Applicant: Amazon Technologies, inc.

Inventor： Ali Ghassan Saidi ,  Adi Habusha ,  Itai Avron ,  Tzachi Zidenberg ,  Ofer Naaman

IPC: G06F9/455 ,  G06F13/24 ,  G06F11/07

Abstract: An interposer circuit is used between an interrupt controller and a processor core to facilitate direct injection of a virtual interrupt into a guest executing on the processor core, even though the interrupt controller does not support the direct injection. The interposer circuit can convert a command received from the interrupt controller for a physical interrupt into another command for a virtual interrupt to make the processor core believe that the processor core has received a virtual interrupt even though the interrupt controller is not able to provide the virtual interrupt. The virtual interrupt can be directly injected into the processor core without the intervention of a hypervisor executing on the processor core.

公开(公告)号：US10824506B1

公开(公告)日：2020-11-03

申请号：US16215222

申请日：2018-12-10

Applicant: Amazon Technologies, Inc.

Inventor： Itai Avron ,  Adi Habusha

IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

Abstract: A method and circuit are disclosed to calculate an error correction code (ECC) and perform a decompression in parallel when reading memory data. There are multiple modes of operation. In a normal parallel mode of operation, the data passes through a decompression engine. Simultaneously, the same data passes through an ECC decode engine. However, if no error is detected, the output of the decode engine is discarded. If there is an ECC error, an error indication is made so that the corresponding data exiting the decompression engine is discarded. The circuit then switches to a serial mode of operation, wherein the ECC decode engine corrects the data and resends the corrected data again through the decompression engine. The circuit is maintained in the serial mode until a decision is made to switch back to the parallel mode, such as when a pipeline of the ECC engine becomes empty.

公开(公告)号：US20190384710A1

公开(公告)日：2019-12-19

申请号：US16110748

申请日：2018-08-23

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Gil Stoler ,  Said Bshara ,  Nafea Bshara

IPC: G06F12/0817 ,  G06F12/0855 ,  G06F12/0831 ,  G11C7/10

Abstract: A method for writing data, the method may include: receiving or generating, by an interfacing module, a data unit coherent write request for performing a coherent write operation of a data unit to a first address; receiving, by the interfacing module and from a circuit that comprises a cache and a cache controller, a cache coherency indicator that indicates that a most updated version of the content stored at the first address is stored in the cache; and instructing, by the interfacing module, the cache controller to invalidate a cache line of the cache that stored the most updated version of the first address without sending the most updated version of the content stored at the first address from the cache to a memory module that differs from the cache if a length of the data unit equals a length of the cache line.

公开(公告)号：US10509758B1

公开(公告)日：2019-12-17

申请号：US15718955

申请日：2017-09-28

Applicant: Amazon Technologies, Inc.

Inventor： Adi Habusha ,  Georgy Zorik Machulsky ,  Nafea Bshara ,  Tal Zilcer

IPC: G06F13/00 ,  G06F13/40 ,  G06F13/42 ,  G06F13/10

Abstract: Provided are systems and methods for hot-plugging emulated peripheral devices (e.g., endpoints) into host devices that either have a hypervisor that does not support virtualized peripheral device or that do not include a hypervisor. In various implementations, a configurable peripheral device can emulate a switch that includes upstream ports and downstream ports. When a new endpoint device is requested, the configurable peripheral device can, using an emulation configuration for the new endpoint device, generate an emulation for the new endpoint device. The configurable peripheral device can connect the endpoint device to a downstream port, and then trigger a hot-plug mechanism, through which the host device can add the new endpoint device to the known hardware of the host device.