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241 条记录 (耗时 0.029 秒)

    Tri-gate patterning using dual layer gate stack
    51.
    发明授权
    Tri-gate patterning using dual layer gate stack 有权
    使用双层栅极堆叠的三栅极图案化

    公开(公告)号：US07745270B2

    公开(公告)日：2010-06-29

    申请号：US12006047

    申请日：2007-12-28

    申请人： Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Been-Yih Jin

    发明人： Uday Shah ,  Brian S. Doyle ,  Jack T. Kavalieros ,  Been-Yih Jin

    IPC分类号： H01L21/84

    CPC分类号： H01L21/823821 ,  H01L29/66795 ,  H01L29/785

    摘要： In general, in one aspect, a method includes forming an n-diffusion fin and a p-diffusion fin in a semiconductor substrate. A high dielectric constant layer is formed over the substrate. A first work function metal layer is created over the n-diffusion fin and a second work function metal layer, thicker than the first, is created over the n-diffusion fin. A silicon germanium layer is formed over the first and second work function metal layers. A polysilicon layer is formed over the silicon germanium layer and is polished. The polysilicon layer over the first work function metal layer is thicker than the polysilicon layer over the second work function metal layer. A hard mask is patterned and used to etch the polysilicon layer and the silicon germanium layer to create gate stacks. The etch rate of the silicon germanium layer is faster over the first work function metal layer.

    摘要翻译： 通常，在一个方面，一种方法包括在半导体衬底中形成n扩散鳍和p扩散鳍。 在衬底上形成高介电常数层。 在n扩散翅片上形成第一功函数金属层，并在n扩散鳍片上形成比第一功函数金属层厚的第二功函数金属层。 在第一和第二功函数金属层上形成硅锗层。 在硅锗层上形成多晶硅层并进行抛光。 第一功函数金属层上的多晶硅层比第二功函数金属层上的多晶硅层厚。 硬掩模被图案化并用于蚀刻多晶硅层和硅锗层以产生栅极堆叠。 硅锗层的蚀刻速率比第一功函数金属层更快。

    Fabrication of germanium nanowire transistors
    52.
    发明授权
    Fabrication of germanium nanowire transistors 有权
    锗纳米线晶体管的制造

    公开(公告)号：US07727830B2

    公开(公告)日：2010-06-01

    申请号：US12006273

    申请日：2007-12-31

    申请人： Been-Yih Jin ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Marko Radosavlievic ,  Robert S. Chau

    发明人： Been-Yih Jin ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Marko Radosavlievic ,  Robert S. Chau

    IPC分类号： H01L21/337

    CPC分类号： H01L29/0665 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/42392 ,  H01L29/66477 ,  H01L29/78684 ,  H01L29/78696

    摘要： In general, in one aspect, a method includes using the Germanium nanowire as building block for high performance logic, memory and low dimensional quantum effect devices. The Germanium nanowire channel and the SiGe anchoring regions are formed simultaneously through preferential Si oxidation of epitaxial Silicon Germanium epi layer. The placement of the germanium nanowires is accomplished using a Si fin as a template and the germanium nanowire is held on Si substrate through SiGe anchors created by masking the two ends of the fins. High dielectric constant gate oxide and work function metals wrap around the Germanium nanowire for gate-all-around electrostatic channel on/off control, while the Germanium nanowire provides high carrier mobility in the transistor channel region. The germanium nanowire transistors enable high performance, low voltage (low power consumption) operation of logic and memory devices.

    摘要翻译： 通常，在一个方面，一种方法包括使用锗纳米线作为高性能逻辑，存储器和低维量子效应器件的构建块。 锗纳米线通道和SiGe锚定区域通过外延硅锗外延层的优先Si氧化同时形成。 使用Si翅片作为模板来实现锗纳米线的放置，并且锗纳米线通过掩蔽翅片的两端而形成的SiGe锚定件保持在Si衬底上。 高介电常数栅极氧化物和功函数金属缠绕在锗纳米线上，用于门极全静电通道开/关控制，而锗纳米线在晶体管沟道区域提供高载流子迁移率。 锗纳米线晶体管可实现逻辑和存储器件的高性能，低电压（低功耗）操作。

    Hetero-Bimos injection process for non-volatile flash memory
    58.
    发明申请
    Hetero-Bimos injection process for non-volatile flash memory 有权
    异质闪存注入过程

    公开(公告)号：US20080237735A1

    公开(公告)日：2008-10-02

    申请号：US11731162

    申请日：2007-03-30

    申请人： Jack T. Kavalieros ,  Suman Datta ,  Robert S. Chau ,  David L. Kencke

    发明人： Jack T. Kavalieros ,  Suman Datta ,  Robert S. Chau ,  David L. Kencke

    IPC分类号： H01L27/06 ,  H01L21/8249

    CPC分类号： H01L21/8249 ,  H01L21/28273 ,  H01L27/0705 ,  H01L29/0821 ,  H01L29/66825 ,  H01L29/73 ,  H01L29/7606 ,  H01L29/7881

    摘要： A hetero-BiMOS injection system comprises a MOSFET transistor formed on a substrate and a hetero-bipolar transistor formed within the substrate. The bipolar transistor can be used to inject charge carriers into a floating gate of the MOSFET transistor. This is done by operating the MOSFET transistor to form an inversion layer in its channel region and operating the bipolar transistor to drive minority charge carriers from the substrate into a floating gate of the MOSFET transistor. The substrate provides a silicon emitter and a silicon germanium containing base for the bipolar transistor. The inversion layer provides a silicon collector for the bipolar transistor.

    摘要翻译： 异质BiMOS注入系统包括形成在衬底上的MOSFET晶体管和形成在衬底内的异质双极晶体管。 双极晶体管可用于将电荷载流子注入MOSFET晶体管的浮置栅极。 这通过操作MOSFET晶体管在其沟道区域中形成反型层并且操作双极晶体管来驱动少数电荷载体从衬底驱动到MOSFET晶体管的浮置栅极。 衬底为双极晶体管提供硅发射极和含硅锗基底。 反型层为双极晶体管提供硅集电极。

    On-chip memory cell and method of manufacturing same
    59.
    发明申请
    On-chip memory cell and method of manufacturing same 审中-公开
    片上存储单元及其制造方法

    公开(公告)号：US20080237678A1

    公开(公告)日：2008-10-02

    申请号：US11729192

    申请日：2007-03-27

    申请人： Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Dinesh Somasekhar ,  Ali Keshavarzi

    发明人： Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Dinesh Somasekhar ,  Ali Keshavarzi

    IPC分类号： H01L27/108 ,  H01L21/336

    CPC分类号： H01L27/10873 ,  H01L27/10826 ,  H01L29/785

    摘要： An on-chip memory cell comprises a tri-gate access transistor (145) and a tri-gate capacitor (155). The on-chip memory cell may be an embedded DRAM on a three-dimensional tri-gate transistor and capacitor structures which is fully compatible with existing tri-gate logic transistor fabrication process. Embodiments of the invention use the high fin aspect ratio and inherently superior surface area of the tri-gate transistors to replace the “trench” capacitor in a commodity DRAM with an inversion mode tri-gate capacitor. The tall sidewalls of the tri-gate transistor provide large enough surface area to provide storage capacitance in a small cell area.

    摘要翻译： 片上存储单元包括三栅极存取晶体管（145）和三栅极电容器（155）。 片上存储器单元可以是三维三栅晶体管上的嵌入式DRAM和与现有三栅逻辑晶体管制造工艺完全兼容的电容器结构。 本发明的实施例使用三栅极晶体管的高翅片长宽比和固有优越的表面积来替代具有反向模式三栅极电容器的商品DRAM中的“沟槽”电容器。 三栅极晶体管的高侧壁提供足够大的表面积，以在小单元区域中提供存储电容。