公开(公告)号：US06638844B1

公开(公告)日：2003-10-28

申请号：US10207549

申请日：2002-07-29

申请人： Purakh Raj Verma ,  Sanford Chu ,  Chit Hwei ,  Lap Chan

发明人： Purakh Raj Verma ,  Sanford Chu ,  Chit Hwei ,  Lap Chan

IPC分类号： H01L2144

CPC分类号： H01L27/08 ,  H01L21/76224 ,  H01L21/823878 ,  H01L27/0617

摘要： A method of reducing substrate coupling and noise for one or more RFCMOS components comprising the following steps. A substrate having a frontside and a backside is provided. One or more RFCMOS components are formed over the substrate. One or more isolation structures are formed within the substrate proximate the one or more RFCOMS components. The backside of the substrate is etched to form respective trenches within the substrate and over at least the one or more isolation structures. The respective trenches are filled with dielectric material whereby the substrate coupling and noise for the one or more RFCMOS components are reduced.

摘要翻译： 一种降低一个或多个RFCMOS组件的衬底耦合和噪声的方法，包括以下步骤。 提供具有前侧和背侧的基板。 在衬底上形成一个或多个RFCMOS部件。 一个或多个隔离结构在靠近一个或多个RFCOMS组件的衬底内形成。 蚀刻衬底的背面以在衬底内并且在至少一个或多个隔离结构上形成相应的沟槽。 相应的沟槽被电介质材料填充，由此降低了一个或多个RFCMOS部件的衬底耦合和噪声。

公开(公告)号：US06461900B1

公开(公告)日：2002-10-08

申请号：US09981438

申请日：2001-10-18

申请人： Ravi Sundaresan ,  Yang Pan ,  James Lee Young Meng ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek

发明人： Ravi Sundaresan ,  Yang Pan ,  James Lee Young Meng ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek

IPC分类号： H01L2100

CPC分类号： H01L21/84 ,  H01L21/823885 ,  H01L27/1203

摘要： A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprises silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain. A gate trench is etched through the NMOS and PMOS sources and channel regions. The gate trench terminates at the NMOS and PMOS drains and exposes the sidewalls of the NMOS and PMOS channel regions. A gate oxide layer is formed overlying the NMOS and PMOS channel regions and lining the gate trench. A polysilicon layer is deposited and etched back to form polysilicon sidewalls and to thereby form gates for the closely-spaced, vertical NMOS and PMOS transistor pair.

摘要翻译： 实现了在集成电路器件中形成紧密间隔的垂直NMOS和PMOS晶体管对的方法。 衬底包括硅注入氧化物（SIMOX），其中氧化物层夹在下层和上层的硅层之间。 离子选择性地注入到上覆硅层的第一部分中以形成用于NMOS晶体管的漏极，沟道区和源极。 漏极直接形成在氧化层的上方，沟道区形成在漏极上方，源极形成在沟道区域的上方。 离子选择性地注入到上层硅层的第二部分中以形成用于PMOS晶体管的漏极，沟道区和源极。 漏极直接形成在氧化层的上方，PMOS沟道区形成在漏极上方，源极形成在沟道区域的上方。 PMOS晶体管漏极与所述NMOS晶体管漏极接触。 通过NMOS和PMOS源极和沟道区域蚀刻栅极沟槽。 栅极沟槽在NMOS和PMOS漏极处终止并暴露NMOS和PMOS沟道区的侧壁。 形成栅极氧化层，覆盖NMOS沟道区和PMOS沟道区，并衬在栅极沟槽。 沉积多晶硅层并回蚀刻以形成多晶硅侧壁，从而形成用于紧密间隔的垂直NMOS和PMOS晶体管对的栅极。

公开(公告)号：US06461887B1

公开(公告)日：2002-10-08

申请号：US10038391

申请日：2002-01-03

申请人： Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung

发明人： Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung

IPC分类号： H01L2100

CPC分类号： H01L21/76232

摘要： A method of forming an inverted staircase shaped STI structure comprising the following steps. A semiconductor substrate having an overlying oxide layer is provided. The substrate having at least a pair of active areas defining an STI region therebetween. The oxide layer is etched a first time within the active areas to form first step trenches. The first step trenches having exposed sidewalls. Continuous side wall spacers are formed on said exposed first step trench sidewalls. The oxide layer is etched X+1 more successive times using the previously formed step side wall spacers as masks to form successive step trenches within the active areas. Each of the successive step trenches having exposed sidewalls and have side wall spacers successively formed on the successive step trench exposed sidewalls. The oxide layer is etched a final time using the previously formed step side wall spacers as masks to form final step trenches exposing the substrate within the active areas. The STI region comprising an inverted staircase shaped STI structure. The step side wall spacers are removed from the X+2 step trenches. A planarized active area silicon structure is formed within the X+2 and final step trenches.

摘要翻译： 一种形成倒置阶梯状STI结构的方法，包括以下步骤。 提供具有上覆氧化物层的半导体衬底。 衬底具有至少一对在其间限定STI区的有源区。 首先在有源区内蚀刻氧化物层以形成第一级沟槽。 第一级沟槽具有暴露的侧壁。 连续的侧壁间隔件形成在所述暴露的第一阶梯沟槽侧壁上。 使用先前形成的步骤侧壁间隔物作为掩模，将氧化物层连续蚀刻X + 1次，以在有效区域内形成连续的台阶沟槽。 每个连续的台阶沟槽具有暴露的侧壁并且具有连续形成在连续的阶梯槽暴露侧壁上的侧壁间隔物。 使用先前形成的步骤侧壁间隔物作为掩模来最后蚀刻氧化物层，以形成在活性区域内暴露衬底的最终步骤沟槽。 STI区域包括倒置的阶梯状STI结构。 从X + 2台阶沟槽中移除台阶侧壁间隔物。 平面化的有源区硅结构形成在X + 2和最后阶梯沟内。

公开(公告)号：US06436774B1

公开(公告)日：2002-08-20

申请号：US09769811

申请日：2001-01-26

申请人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

发明人： James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Quek ,  Ravi Sundaresan ,  Yang Pan

IPC分类号： H01L21336

CPC分类号： H01L21/28194 ,  H01L29/42376 ,  H01L29/512 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66583

摘要： A method for forming a gate dielectric having regions with different dielectric constants. A low-K dielectric layer is formed over a semiconductor structure. A dummy dielectric layer is formed over the low-K dielectric layer. The dummy dielectric layer and low-K dielectric layer are patterned to form an opening. The dummy dielectric layer is isontropically etched selectively to the low-K dielectric layer to form a stepped gate opening. A high-K dielectric layer is formed over the dummy dielectric and in the stepped gate opening. A gate electrode is formed on the high-K dielectric layer.

公开(公告)号：US06403485B1

公开(公告)日：2002-06-11

申请号：US09846177

申请日：2001-05-02

申请人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Lee Yong Meng ,  Ying Keung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

发明人： Elgin Quek ,  Ravi Sundaresan ,  Yang Pan ,  James Lee Yong Meng ,  Ying Keung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan

IPC分类号： H01L21302

CPC分类号： H01L21/76895

摘要： A method of forming a pseudo-SOI device having elevated source/drain (S/D) regions that can be extended for use as local interconnect is described. Shallow trench isolation (STI) regions separating adjacent active regions are provided within a semiconductor substrate. Polysilicon gate electrodes and associated SID extensions are fabricated in and on the substrate in the active regions wherein a hard mask layer overlies each of the gate electrodes. Dielectric spacers are formed on sidewalls of each of the gate electrodes. A polysilicon layer is deposited overlying the gate electrodes and the substrate. The polysilicon layer is polished back with a polish stop at the hard mask layer. The polysilicon layer is etched back whereby the polysilicon layer is recessed with respect to the gate electrodes. Thereafter, the polysilicon layer is etched away overlying the STI regions where a separation between adjacent active areas is desired. If a local interconnect is desired between adjacent active areas, the polysilicon layer is not etched away overlying the STI region separating those active areas. The hard mask layer is removed. Ions are implanted and driven in to form elevated S/D regions within the polysilicon layer adjacent to the gate electrodes to complete formation of transistors having elevated S/D regions.

摘要翻译： 描述了一种形成具有可扩展的用于局部互连的源/漏（S / D）区域较高的伪SOI器件的方法。 分离相邻有源区的浅沟槽隔离（STI）区域设置在半导体衬底内。 多晶硅栅极电极和相关的SID延伸部分在其中硬掩模层覆盖每个栅极电极的有源区域内和衬底上制造。 在每个栅电极的侧壁上形成电介质间隔物。 沉积覆盖栅电极和衬底的多晶硅层。 在硬掩模层上用抛光光阑抛光多晶硅层。 多晶硅层被回蚀，由此多晶硅层相对于栅电极凹陷。 此后，将多晶硅层蚀刻掉，覆盖STI区域，其中期望相邻的有源区域之间的间隔。 如果在相邻的有源区域之间需要局部互连，则多晶硅层不会被覆盖在分离这些有源区域的STI区域之上。 去除硬掩模层。 离子被植入和驱动以在与栅电极相邻的多晶硅层内形成升高的S / D区，以完成具有升高的S / D区的晶体管的形成。

公开(公告)号：US06403484B1

公开(公告)日：2002-06-11

申请号：US09803187

申请日：2001-03-12

申请人： Victor Seng Keong Lim ,  Lap Chan ,  James Lee ,  Chen Feng ,  Wang Ling Goh

发明人： Victor Seng Keong Lim ,  Lap Chan ,  James Lee ,  Chen Feng ,  Wang Ling Goh

IPC分类号： H01L2100

CPC分类号： H01L21/31056 ,  H01L21/31053 ,  H01L21/76229

摘要： A method of forming shallow trench isolations is described. A plurality of isolation trenches are etched through a first etch stop layer into the underlying semiconductor substrate. An oxide layer is deposited over the first etch stop layer and within the isolation trenches using a high density plasma chemical vapor deposition process (HDP-CVD) wherein after the oxide layer fills the isolation trenches, the deposition component is discontinued while continuing the sputtering component until corners of the first etch stop layer are exposed at edges of the isolation trenches whereby the oxide layer within the isolation trenches is disconnected from the oxide layer overlying the first etch stop layer. Thereafter, a second etch stop layer is deposited overlying the oxide layer within the isolation trenches, the oxide layer overlying the first etch stop layer, and the exposed first etch stop layer corners. The second etch stop layer is polished away until the oxide layer overlying the first etch stop layer is exposed. The exposed oxide layer overlying the first etch stop layer is removed. The first and second etch stop layers are removed to complete the planarized shallow trench isolation regions in the manufacture of an integrated circuit device.

摘要翻译： 描述了形成浅沟槽隔离的方法。 通过第一蚀刻停止层将多个隔离沟槽蚀刻到下面的半导体衬底中。 使用高密度等离子体化学气相沉积工艺（HDP-CVD）在第一蚀刻停止层和隔离沟槽内沉积氧化物层，其中在氧化物层填充隔离沟槽之后，沉积组分被中断，同时继续溅射组分 直到第一蚀刻停止层的角部暴露在隔离沟槽的边缘处，由此隔离沟槽内的氧化物层与覆盖在第一蚀刻停止层上的氧化物层断开。 此后，沉积在隔离沟槽内的氧化物层上的第二蚀刻停止层，覆盖在第一蚀刻停止层上的氧化物层和暴露的第一蚀刻停止层拐角。 将第二蚀刻停止层抛光，直到暴露出覆盖在第一蚀刻停止层上的氧化物层。 去除覆盖在第一蚀刻停止层上的暴露的氧化物层。 去除第一和第二蚀刻停止层以在集成电路器件的制造中完成平坦化的浅沟槽隔离区。

公开(公告)号：US06355563B1

公开(公告)日：2002-03-12

申请号：US09798652

申请日：2001-03-05

申请人： Randall Cher Liang Cha ,  Alex See ,  Yeow Kheng Lim ,  Tae Jong Lee ,  Lap Chan

发明人： Randall Cher Liang Cha ,  Alex See ,  Yeow Kheng Lim ,  Tae Jong Lee ,  Lap Chan

IPC分类号： H01L2144

CPC分类号： H01L21/76802 ,  H01L21/76825 ,  H01L21/76831 ,  H01L21/76832

摘要： A method to integrate low dielectric constant dielectric materials with copper metallization is described. A metal line is provided overlying a semiconductor substrate and having a nitride capping layer thereover. A polysilicon layer is deposited over the nitride layer and patterned to form dummy vias. A dielectric liner layer is conformally deposited overlying the nitride layer and dummy vias. A dielectric layer having a low dielectric constant is spun-on overlying the liner layer and covering the dummy vias. The dielectric layer is polished down whereby the dummy vias are exposed. Thereafter, the dielectric layer is cured whereby a cross-linked surface layer is formed. The dummy vias are removed thereby exposing a portion of the nitride layer within the via openings. The exposed nitride layer is removed. The via openings are filled with a copper layer which is planarized to complete copper metallization in the fabrication of an integrated circuit device.

摘要翻译： 描述了一种将低介电常数电介质材料与铜金属化相结合的方法。 金属线设置在半导体衬底上并且在其上具有氮化物覆盖层。 多晶硅层沉积在氮化物层上并被图案化以形成虚拟通孔。 电介质衬垫层共形沉积在氮化物层和虚拟通孔之上。 将具有低介电常数的介电层旋涂在衬层上并覆盖虚拟通孔。 抛光电介质层，从而暴露虚拟通孔。 此后，电介质层被固化，由此形成交联表面层。 去除虚设通孔，从而将通孔的一部分氮化物层露出。 去除暴露的氮化物层。 通孔开口填充有铜层，该铜层在集成电路器件的制造中被平坦化以完成铜金属化。

公开(公告)号：US06348385B1

公开(公告)日：2002-02-19

申请号：US09726256

申请日：2000-11-30

申请人： Randall Cher Liang Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Chee Tee Chua

发明人： Randall Cher Liang Cha ,  Tae Jong Lee ,  Alex See ,  Lap Chan ,  Chee Tee Chua

IPC分类号： H01L21336

CPC分类号： H01L29/66545 ,  H01L21/2255 ,  H01L21/28167 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66537 ,  H01L29/66553 ,  H01L29/7834

摘要： The method for a transistor using a replacement gate process that has a doped low-K dielectric spacer that lowers the junction capacitance. A dummy gate is formed over a substrate. Ions are implanted into the substrate using the dummy gate as an implant mask to form source and drain regions. A masking layer is formed on the substrate over the source and drain regions. We remove the dummy gate. Doped low k spacers are formed on the sidewalls of the masking layer. The doped spacers are heated to diffuse dopant into the substrate to form lightly doped drain (LDD regions). We form a high k gate dielectric layer over the masking layer. A gate layer is formed over the high K dielectric layer. The gate layer is chemical-mechanical polished (CMP) to form a gate over the high k dielectric layer and to remove the gate layer over the masking layer.

摘要翻译： 使用具有降低结电容的掺杂低K电介质间隔物的替代栅极工艺的晶体管的方法。 在基板上形成虚拟栅极。 使用伪栅极作为注入掩模将离子注入到衬底中以形成源区和漏区。 在源极和漏极区上的衬底上形成掩模层。 我们删除虚拟门。 在掩蔽层的侧壁上形成掺杂的低k间隔物。 掺杂的间隔物被加热以将掺杂剂扩散到衬底中以形成轻掺杂漏极（LDD区）。 我们在掩模层上形成一个高k栅介质层。 在高K电介质层上形成栅极层。 栅极层是化学机械抛光（CMP），以在高k电介质层上形成栅极，并且去除掩模层上的栅极层。

公开(公告)号：US06303449B1

公开(公告)日：2001-10-16

申请号：US09713835

申请日：2000-11-16

申请人： Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Kiok Boone Quek ,  Ravi Sundaresan

发明人： Yang Pan ,  James Yong Meng Lee ,  Ying Keung Leung ,  Yelehanka Ramachandramurthy Pradeep ,  Jia Zhen Zheng ,  Lap Chan ,  Elgin Kiok Boone Quek ,  Ravi Sundaresan

IPC分类号： H01L21336

CPC分类号： H01L29/66583 ,  H01L21/2257 ,  H01L29/66492

摘要： A method of manufacturing a self aligned elevated source/drain (S/D). A first insulating layer is formed over a substrate. The first insulating layer having at least a gate opening and source/drain (S/D) openings adjacent to the gate opening. Spacer portions of the first insulating layer define the gate opening. A gate dielectric layer is formed over the substrate in the gate opening. A conductive layer is formed over the substrate. The conductive layer fills the gate opening and the source/drain (S/D) openings. The conductive layer is doped with dopants. The conductive layer is planarized to form a gate over the gate dielectric layer and filling the gate opening and filling the source/drain (S/D) opening to form elevated source/drain (S/D) regions. The conductive layer is preferably planarized so that the top surface of the conductive layer is level with the top surface of the first insulating layer. The spacer portions are removed to form spacer openings. LDD regions are formed in the substrate in the spacer opening. A dielectric layer is formed over the substrate filling the spacer openings. Source/drain (S/D) regions are formed in the substrate under the elevated source/drain (S/D) regions.

摘要翻译： 制造自对准提升源/漏（S / D）的方法。 第一绝缘层形成在衬底上。 第一绝缘层至少具有与开口相邻的栅极开口和源极/漏极（S / D）开口。 第一绝缘层的间隔部分限定了开口。 在栅极开口中的衬底上方形成栅极电介质层。 导电层形成在衬底上。 导电层填充栅极开口和源极/漏极（S / D）开口。 导电层掺杂有掺杂剂。 导电层被平坦化以在栅极介电层上形成栅极，并填充栅极开口并填充源极/漏极（S / D）开口以形成升高的源极/漏极（S / D）区域。 导电层优选被平坦化，使得导电层的顶表面与第一绝缘层的顶表面平齐。 间隔部分被去除以形成间隔开口。 LDD区域形成在衬垫开口中的衬底中。 介质层形成在填充间隔开口的衬底上。 在升高的源极/漏极（S / D）区域的衬底中形成源/漏（S / D）区。

公开(公告)号：US06300172B1

公开(公告)日：2001-10-09

申请号：US09409887

申请日：1999-10-01

申请人： Ting Cheong Ang ,  Shyue Pong Quek ,  Lap Chan ,  Sang Yee Loong

发明人： Ting Cheong Ang ,  Shyue Pong Quek ,  Lap Chan ,  Sang Yee Loong

IPC分类号： H01L2100

CPC分类号： H01L21/76264 ,  H01L21/76281

摘要： A method of fabricating an SOI transistor device comprises the following steps. a silicon semiconductor structure is provided. A silicon oxide layer is formed over the silicon semiconductor structure. A silicon-on-insulator layer is formed over the oxide layer. A well is implanted in the silicon-on-insulator layer. A gate oxide layer is grown over the silicon-on-insulator layer. A polysilicon layer is deposited over the gate oxide layer. The polysilicon layer, gate oxide layer, and silicon oxide layer are patterned and etched to form trenches. The trenches are filled with an isolation material to at least a level even with a top surface of the polysilicon layer to form raised shallow trench isolation regions (STIs). The polysilicon layer is patterned and the non-gate portions are removed polysilicon adjacent the raised STIs forming a gate conductor between the raised STIs with the gate conductor and said raised STIs having exposed sidewalls. The gate oxide layer is removed between the gate conductor and the raised STIs, and outboard of the raised STIs. The source and drain are formed in the silicon-on-insulator layer adjacent the gate spacers. Silicide regions may then be formed on the source and drain.

摘要翻译： 制造SOI晶体管器件的方法包括以下步骤。 提供硅半导体结构。 在硅半导体结构上形成氧化硅层。 在氧化物层上形成绝缘体上硅层。 将阱注入绝缘体上硅层中。 栅氧化层生长在绝缘体上硅层上。 在栅极氧化物层上沉积多晶硅层。 对多晶硅层，栅极氧化物层和氧化硅层进行图案化和蚀刻以形成沟槽。 沟槽用隔离材料填充至少甚至具有多晶硅层的顶表面的水平以形成凸起的浅沟槽隔离区域（STI）。 多晶硅层被图案化，并且非栅极部分去除与凸起的STI相邻的多晶硅，其在栅极导体和所述凸起的STI具有暴露的侧壁之间在凸起的STI之间形成栅极导体。 栅极氧化物层在栅极导体和凸起的STI之间以及凸起的STIs的外侧被移除。 源极和漏极形成在邻近栅极间隔物的绝缘体上硅层中。 然后可以在源极和漏极上形成硅化物区域。