公开(公告)号：US07636262B2

公开(公告)日：2009-12-22

申请号：US11923691

申请日：2007-10-25

申请人： Kyu-Hyoun Kim ,  Paul W. Coteus

发明人： Kyu-Hyoun Kim ,  Paul W. Coteus

IPC分类号： G11C7/10

CPC分类号： G06F13/1689 ,  G06F11/1004

摘要： A memory system having a memory element chip (DRAM) and a memory controller chips having a plurality of drivers and receivers and latches for transferred data. For writes clocks, write data and write for CRC (cyclic redundancy checks) is transferred to the DRAM from the memory controller and latched for error checking. The reads are clocked and the read data is received and transferred to a read data latch with also receives a clocked read strobe for verification of data integrity from DRAM. Each chip has a bi-functional pin that acts as a shared CRC pin during write and acts as a shared strobe pin during READ. Data transfers with the CRC signal and DQS signal are transferred across two paths CRC0/DQS and CRC1/DQS1. One could also transfer the CRC signal across one path with only the CRC0/DQS signal. Read operations have no CRC, and have no need for CRC because transfer errors during read can be detected by memory error correction coding (ECC). Write data provides source synchronous I/O data to said memory element chip needed for modem high speed memory communications.

摘要翻译： 具有存储元件芯片（DRAM）的存储器系统和具有用于传送数据的多个驱动器和接收器以及锁存器的存储器控​​制器芯片。 对于写时钟，写入数据和写入CRC（循环冗余校验）从存储器控制器传送到DRAM，并锁存进行错误检查。 读取被计时，并且读取的数据被接收并被传送到读取数据锁存器，同时还接收用于从DRAM确认数据完整性的时钟读选通脉冲。 每个芯片都有一个双功能引脚，在写入期间充当共享的CRC引脚，并在读取期间充当共享的选通引脚。 具有CRC信号和DQS信号的数据传输通过两个路径CRC0 / DQS和CRC1 / DQS1传送。 也可以通过CRC0 / DQS信号在一个路径上传送CRC信号。 读操作没有CRC，并且不需要CRC，因为可以通过存储器纠错编码（ECC）来检测读取期间的传输错误。 写入数据将源同步I / O数据提供给调制解调器高速存储器通信所需的所述存储器元件芯片。

公开(公告)号：US07598762B2

公开(公告)日：2009-10-06

申请号：US11243369

申请日：2005-10-04

申请人： Gyung-Su Byun ,  Kyu-Hyoun Kim ,  Woo-Seop Kim

发明人： Gyung-Su Byun ,  Kyu-Hyoun Kim ,  Woo-Seop Kim

IPC分类号： G01R31/26 ,  G01R31/02

CPC分类号： G11C29/50008 ,  G11C7/1048 ,  G11C29/02 ,  G11C29/022 ,  G11C29/025 ,  G11C29/028 ,  G11C2029/5006 ,  G11C2207/105

摘要： A semiconductor driver circuit includes impedance units for generating impedances at data pads, independently of each-other. Thus, signal swing widths of data signals generated at the data pads may be easily adjusted to be substantially equal for high operating speed. The semiconductor driver circuit also includes switching units for uncoupling at least one of the impedance units from at least one of the data pads for enhanced testing of the data pads.

摘要翻译： 半导体驱动器电路包括用于在数据焊盘处产生阻抗的阻抗单元，其独立于彼此。 因此，在数据焊盘处产生的数据信号的信号摆动宽度可以容易地调整为在高操作速度下基本相等。 半导体驱动器电路还包括用于从至少一个数据焊盘解耦至少一个阻抗单元的开关单元，用于增强数据焊盘的测试。

公开(公告)号：US07528668B2

公开(公告)日：2009-05-05

申请号：US11594448

申请日：2006-11-08

申请人： Jin-Young Kim ,  Kyu-Hyoun Kim

发明人： Jin-Young Kim ,  Kyu-Hyoun Kim

IPC分类号： H03K5/04 ,  H03B1/00 ,  H03L7/08

CPC分类号： H03F3/45183 ,  H03F2203/45371 ,  H03K5/1565 ,  H03K2005/00052 ,  H03L7/08 ,  H03L7/0812 ,  H03L7/0996

摘要： A differential amplifier includes an input stage, a biasing unit and a load unit. The input stage receives a first phase signal and at least two phase signals among odd-numbered phase signals, wherein an average of phases of the at least two phase signals has a phase difference of substantially 180 degrees from the first phase signal. The biasing unit is coupled between the input stage and a first power voltage. The load unit is coupled between the input stage and a second power voltage, and configured to output a differential output signal based on differentially amplifying of the first phase signal and the at least two phase signals. Therefore, a duty cycle distortion in an output signal of a duty cycle correction circuit can be prevented.

摘要翻译： 差分放大器包括输入级，偏置单元和负载单元。 输入级在奇数相位信号中接收第一相位信号和至少两个相位信号，其中至少两个相位信号的相位平均值具有与第一相位信号基本上180度的相位差。 偏压单元耦合在输入级和第一电源电压之间。 负载单元耦合在输入级和第二电源电压之间，并且被配置为基于第一相位信号和至少两个相位信号的差分放大来输出差分输出信号。 因此，可以防止占空比校正电路的输出信号中的占空比失真。

公开(公告)号：US07518539B2

公开(公告)日：2009-04-14

申请号：US11805135

申请日：2007-05-22

申请人： June-Soo Han ,  Kyu-Hyoun Kim

发明人： June-Soo Han ,  Kyu-Hyoun Kim

IPC分类号： H03M1/12

CPC分类号： H03M1/1245

摘要： For signal processing such as in an image sensor, a CDS (correlated double sampling) unit generates a first CDS signal from a first set of input signals at a predetermined node. In addition, a conversion unit converts a second CDS signal into a respective converted signal concurrently as the CDS unit generates the fist CDS signal. The second CDS signal is determined from a second set of input signals previously generated at the predetermined node.

摘要翻译： 对于诸如图像传感器中的信号处理，CDS（相关双采样）单元从预定节点处的第一组输入信号产生第一CDS信号。 此外，当CDS单元产生第一CDS信号时，转换单元将第二CDS信号同时转换为相应的转换信号。 第二个CDS信号是从预定节点以​​前生成的第二组输入信号确定的。

公开(公告)号：US07336554B2

公开(公告)日：2008-02-26

申请号：US11258565

申请日：2005-10-25

申请人： Kyu-Hyoun Kim ,  Chang-Hyun Kim

发明人： Kyu-Hyoun Kim ,  Chang-Hyun Kim

IPC分类号： G11C7/00 ,  G11C7/10

CPC分类号： G11C5/066 ,  H04Q2213/13103 ,  H04Q2213/13292 ,  H04Q2213/1332 ,  H04Q2213/13322

摘要： A semiconductor memory device includes an IO circuit for receiving or outputting command signals, address signals and data which are serialized and an IO signal control circuit for parallel converting the serialized command signals, address signals and data inputted through the IO circuit and applying the parallel converted signals to an internal portion and serial converting parallel data applied from the internal portion and outputting the serial converted data to the IO circuit.

摘要翻译： 一种半导体存储器件包括用于接收或输出串行化的命令信号，地址信号和数据的IO电路，以及用于并行转换串行化命令信号的IO信号控制电路，地址信号和通过IO电路输入的数据并且将并行转换 发送到内部部分，并串行转换从内部部分应用的并行数据，并将串行转换数据输出到IO电路。

公开(公告)号：US20070204199A1

公开(公告)日：2007-08-30

申请号：US11705151

申请日：2007-02-12

申请人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

发明人： Hoe-Ju Chung ,  Kyu-Hyoun Kim

IPC分类号： G11C29/00

CPC分类号： H03M13/29 ,  G06F11/08 ,  G06F11/1008 ,  G11C7/1006 ,  G11C29/42 ,  G11C2029/0411 ,  G11C2207/104

摘要： A semiconductor memory device and a memory system including the same are provided. The semiconductor memory device may include a first memory cell array block generating first data, a second memory cell array block generating second data, and first and second error detection code generators. The first error detection code generator may generate a first error detection code and may combine a portion of bits of the first error detection code with a portion of bits of a second error detection code to generate a first final error detection signal. The second error detection code generator may generate the second error detection code and may combine the remaining bits other than the portion of bits of the second error detection code with the remaining bits other than the portion of bits of the first error detection code to generate a second final error detection signal.

摘要翻译： 提供一种半导体存储器件和包括该半导体存储器件的存储器系统。 半导体存储器件可以包括产生第一数据的第一存储单元阵列块，产生第二数据的第二存储单元阵列块，以及第一和第二错误检测码发生器。 第一错误检测码发生器可以产生第一错误检测码，并且可以将第一错误检测码的位的一部分与第二错误检测码的位的一部分组合以产生第一最终错误检测信号。 第二错误检测码发生器可以产生第二错误检测码，并且可以将除了第二错误检测码的位的部分之外的其余位与除第一错误检测码的位的部分之外的其余位组合以产生 第二最终错误检测信号。

公开(公告)号：US07135935B2

公开(公告)日：2006-11-14

申请号：US10841866

申请日：2004-05-06

申请人： Kyu-Hyoun Kim

发明人： Kyu-Hyoun Kim

IPC分类号： H03K3/03

CPC分类号： H03K3/012 ,  H03K3/0315 ,  H03K3/0322 ,  Y10S331/03

摘要： A ring oscillator has a first logic circuit forming a first loop. The ring oscillator also has a second logic circuit forming a second loop, such that phase interpolation occurs at a node common to the first and second loops. The phase interpolation results in an output signal with a high frequency.

摘要翻译： 环形振荡器具有形成第一回路的第一逻辑电路。 环形振荡器还具有形成第二回路的第二逻辑电路，使得相位插值发生在第一和第二回路共同的节点处。 相位插值导致具有高频率的输出信号。

公开(公告)号：US20050057316A1

公开(公告)日：2005-03-17

申请号：US10841866

申请日：2004-05-06

申请人： Kyu-Hyoun Kim

发明人： Kyu-Hyoun Kim

IPC分类号： H03K3/0231 ,  H03K3/012 ,  H03K3/03 ,  H03B1/00

CPC分类号： H03K3/012 ,  H03K3/0315 ,  H03K3/0322 ,  Y10S331/03

摘要： A ring oscillator has a first logic circuit forming a first loop. The ring oscillator also has a second logic circuit forming a second loop, such that phase interpolation occurs at a node common to the first and second loops. The phase interpolation results in an output signal with a high frequency.

摘要翻译： 环形振荡器具有形成第一回路的第一逻辑电路。 环形振荡器还具有形成第二回路的第二逻辑电路，使得相位插值发生在第一和第二回路共同的节点处。 相位插值导致具有高频率的输出信号。

公开(公告)号：US06847559B2

公开(公告)日：2005-01-25

申请号：US10611255

申请日：2003-07-01

申请人： Reum Oh ,  Woo-Seop Jeong ,  Kyu-Hyoun Kim

发明人： Reum Oh ,  Woo-Seop Jeong ,  Kyu-Hyoun Kim

IPC分类号： H03K19/0175 ,  G11C7/10 ,  G11C11/406 ,  G11C11/407 ,  G11C11/409 ,  G11C11/4093 ,  G11C7/00

CPC分类号： G11C7/1084 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4093

摘要： The present invention discloses an input buffer circuit of a synchronous semiconductor memory device comprising a differential amplifier type input buffer and a low current type input buffer, wherein the differential amplifier type input buffer is operated in a normal mode, and the low current type input buffer is operated in a self-refresh mode, thereby decreasing the current flowing through the input buffer in the self-refresh mode. According to the input buffer of the synchronous semiconductor memory device, the current flowing through the input buffer in the self-refresh mode is very small, therefore the power consumption of the synchronous semiconductor memory device can be reduced.

摘要翻译： 本发明公开了一种包括差分放大器型输入缓冲器和低电流型输入缓冲器的同步半导体存储器件的输入缓冲电路，其中差分放大器型输入缓冲器以正常模式工作，低电流型输入缓冲器 在自刷新模式下操作，从而在自刷新模式下减少流过输入缓冲器的电流。 根据同步半导体存储器件的输入缓冲器，在自刷新模式中流过输入缓冲器的电流非常小，因此可以降低同步半导体存储器件的功耗。

公开(公告)号：US08823162B2

公开(公告)日：2014-09-02

申请号：US13462994

申请日：2012-05-03

申请人： Jimmy G. Foster, Sr. ,  Kyu-Hyoun Kim

发明人： Jimmy G. Foster, Sr. ,  Kyu-Hyoun Kim

IPC分类号： H01L23/04

CPC分类号： H01L25/0657 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2924/19051

摘要： An integrated circuit die stack including a first integrated circuit die mounted upon a substrate, the first die including pass-through vias (‘PTVs’) composed of conductive pathways through the first die with no connection to any circuitry on the first die; and a second integrated circuit die, identical to the first die, shifted in position with respect to the first die and mounted upon the first die, with the PTVs in the first die connecting signal lines from the substrate through the first die to through silicon vias (‘TSVs’) in the second die composed of conductive pathways through the second die connected to electronic circuitry on the second die; with the TSVs and PTVs disposed upon each identical die so that the positions of the TSVs and PTVs on each identical die are translationally compatible with respect to the TSVs and PTVs on the other identical die.

摘要翻译： 一种集成电路管芯堆叠，其包括安装在衬底上的第一集成电路管芯，所述第一管芯包括由通过所述第一管芯的导电通路组成的通孔（“PTV”），其没有连接到所述第一管芯上的任何电路; 以及与第一裸片相同的第二集成电路裸片相对于第一裸片位置偏移并安装在第一裸片上，第一裸片中的PTV将来自衬底的信号线通过第一裸片连接到硅通孔 （“TSV”），其由通过第二管芯的导电通路组成，连接到第二管芯上的电子电路; 其中TSV和PTV设置在每个相同的管芯上，使得每个相同管芯上的TSV和PTV的位置相对于另一个相同管芯上的TSV和PTV平移兼容。