公开(公告)号：US6051459A

公开(公告)日：2000-04-18

申请号：US803730

申请日：1997-02-21

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Frederick N. Hause ,  Derick J. Wristers

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Frederick N. Hause ,  Derick J. Wristers

IPC分类号： H01L21/8238

CPC分类号： H01L21/823842

摘要： A method of making N-channel and P-channel IGFETs is disclosed. The method includes providing a semiconductor substrate with N-type and P-type active regions, forming a gate material over the N-type and P-type active regions, forming a first masking layer over the gate material, wherein the first masking layer includes an opening above a first portion of the gate material over the P-type active region, and the first masking layer covers a second portion of the gate material over the N-type active region, introducing an N-type dopant into the first portion of the gate material without introducing the N-type dopant into the second portion of the gate material, applying a thermal cycle to drive-in and activate the N-type dopant in the first portion of the gate material before introducing any doping into the second portion of the gate material, before introducing any source/drain doping into the N-type active region, and before introducing any source/drain doping into the P-type active region, forming a second masking layer over the gate material, wherein the second masking layer covers portions of the first and second portions of the gate material, applying an etch to form first and second gates from unetched portions of the first and second portions of the gate material, respectively, and forming an N-type source and drain in the P-type active region and forming a P-type source and drain in the N-type active region. Advantageously, a dopant in the gate for the N-channel IGFET can be driven-in and activated at a relatively high temperature without subjecting any source/drain doping to this temperature.

摘要翻译： 公开了制造N沟道和P沟道IGFET的方法。 该方法包括提供具有N型和P型有源区的半导体衬底，在N型和P型有源区上形成栅极材料，在栅极材料上形成第一掩模层，其中第一掩模层包括 在P型有源区上方的栅极材料的第一部分上方的开口，并且第一掩模层覆盖N型有源区上的栅极材料的第二部分，将N型掺杂剂引入到第一部分 栅极材料，而不将N型掺杂剂引入栅极材料的第二部分中，在引入任何掺杂到第二部分之前施加热循环以驱动和激活栅极材料的第一部分中的N型掺杂剂 在向N型有源区域引入任何源极/漏极掺杂之前，在向P型有源区域引入任何源极/漏极掺杂之前，在栅极材料上形成第二掩模层， 在第二掩模层中，分别覆盖栅极材料的第一和第二部分的部分，施加蚀刻以分别从栅极材料的第一和第二部分的未蚀刻部分形成第一和第二栅极，并形成N型源极 并在P型有源区中漏极，并在N型有源区中形成P型源极和漏极。 有利的是，用于N沟道IGFET的栅极中的掺杂剂可以被驱入并在相对较高的温度下被激活，而不会对该温度进行任何源极/漏极掺杂。

公开(公告)号：US6048803A

公开(公告)日：2000-04-11

申请号：US914658

申请日：1997-08-19

申请人： Mark I. Gardner ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Daniel Kadosh

IPC分类号： H01L21/316 ,  H01L21/768 ,  H01L21/441

CPC分类号： H01L21/02131 ,  H01L21/02164 ,  H01L21/02321 ,  H01L21/02351 ,  H01L21/31629 ,  H01L21/76801

摘要： A semiconductor device having relatively low permittivity fluorine bearing oxide between conductive lines and a method for fabricating such a device is provided. At least two adjacent conductive lines are formed over a substrate. An oxide layer is formed between the adjacent conductive lines. A mask is formed over the oxide layer and selectively removed to expose a portion of the oxide layer between the adjacent conductive lines. A fluorine bearing species is implanted into the exposed portion of the oxide layer to reduce the permittivity of the oxide layer between the adjacent conductive lines. The permittivity or dielectric constant of the oxide layer between the adjacent conductive lines can, for example, be reduced from about 3.9 to 4.2 to about 3.0 to 3.5.

摘要翻译： 提供了一种在导线之间具有较低介电常数含氟氧化物的半导体器件及其制造方法。 在衬底上形成至少两个相邻的导线。 在相邻的导线之间形成氧化物层。 掩模形成在氧化物层的上方并被选择性地去除以暴露相邻导电线之间的氧化物层的一部分。 将含氟物质注入到氧化物层的暴露部分中以降低相邻导电线之间的氧化物层的介电常数。 相邻导电线之间的氧化物层的介电常数或介电常数例如可以从约3.9至4.2降低至约3.0至3.5。

公开(公告)号：US6037629A

公开(公告)日：2000-03-14

申请号：US28895

申请日：1998-02-24

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Jon D. Cheek

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Jon D. Cheek

IPC分类号： H01L21/336 ,  H01L21/76 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L29/66583 ,  H01L21/76 ,  H01L29/66613 ,  H01L29/66621 ,  H01L29/7834

摘要： An IGFET with a gate electrode in a transistor trench adjacent to an isolation trench is disclosed. The trenches are formed in a semiconductor substrate. A gate insulator is on a bottom surface of the transistor trench, insulative spacers are adjacent to opposing sidewalls of the transistor trench, and the gate electrode is on the gate insulator and spacers and is electrically isolated from the substrate. Substantially all of the gate electrode is within the transistor trench. A source and drain in the substrate are beneath and adjacent to the bottom surface of the transistor trench. The isolation trench is filled with an insulator and provides device isolation for the IGFET. Advantageously, the trenches are formed simultaneously using a single etch step.

摘要翻译： 公开了一种在与隔离沟槽相邻的晶体管沟槽中具有栅电极的IGFET。 沟槽形成在半导体衬底中。 栅极绝缘体位于晶体管沟槽的底表面上，绝缘间隔物与晶体管沟槽的相对的侧壁相邻，并且栅极电极位于栅极绝缘体和间隔物上，并与衬底电隔离。 基本上所有的栅电极都在晶体管沟槽内。 衬底中的源极和漏极在晶体管沟槽的底表面下方并且邻近晶体管沟槽的底表面。 绝缘体填充绝缘体，并为IGFET提供器件隔离。 有利地，使用单个蚀刻步骤同时形成沟槽。

公开(公告)号：US6027964A

公开(公告)日：2000-02-22

申请号：US905681

申请日：1997-08-04

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Michael Duane

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Michael Duane

IPC分类号： H01L21/02 ,  H01L21/266 ,  H01L21/336 ,  H01L27/06 ,  H01L21/8234

CPC分类号： H01L28/20 ,  H01L21/266 ,  H01L27/0629 ,  H01L29/66659

摘要： A method of making an IGFET with a selectively doped gate in combination with a protected resistor includes the steps of providing a semiconductor substrate with an active region and a resistor region, forming a gate over the active region, forming a diffused resistor in the resistor region, forming an insulating layer over the active region and the resistor region, forming a masking layer over the insulating layer that includes an opening above a first portion of the gate and covers the resistor region and a second portion of the gate, applying an etch using the masking layer as an etch mask to remove the insulating layer above the first portion of the gate so that an unetched portion of the insulating layer forms a gate-protect insulator over the second portion of the gate and another unetched portion of the insulating layer forms a resistor-protect insulator over the diffused resistor, and forming a source and a drain in the active region including at least partially doping the source and the drain during a doping step that provides more doping for the first portion of the gate than for the second portion of the gate after forming the masking layer. In this manner, the masking layer can provide both an etch mask for the resistor-protect insulator and an implant mask for selectively doping the gate.

摘要翻译： 制造具有选择性掺杂栅极的IGFET与受保护电阻器组合的方法包括以下步骤：为半导体衬底提供有源区域和电阻器区域，在有源区域上形成栅极，在电阻器区域中形成扩散电阻器 在所述有源区和所述电阻区上方形成绝缘层，在所述绝缘层上形成掩模层，所述绝缘层包括在所述栅极的第一部分上方的开口，并且覆盖所述电阻器区域和所述栅极的第二部分，使用 掩模层作为蚀刻掩模，以去除栅极的第一部分之上的绝缘层，使得绝缘层的未蚀刻部分在栅极的第二部分上形成栅极保护绝缘体，并且形成绝缘层的另一个未蚀刻部分 在所述扩散电阻器上方的电阻保护绝缘体，以及在所述有源区域中形成至少部分掺杂所述酸的源极和漏极 在掺杂步骤中，在形成掩模层之后，栅极的第一部分比栅极的第二部分提供更多的掺杂。 以这种方式，掩模层可以提供用于电阻器保护绝缘体的蚀刻掩模和用于选择性地掺杂栅极的注入掩模。

公开(公告)号：US5970375A

公开(公告)日：1999-10-19

申请号：US851086

申请日：1997-05-03

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Thomas E. Spikes, Jr.

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Thomas E. Spikes, Jr.

IPC分类号： H01L21/768 ,  H01L21/336

CPC分类号： H01L21/76895

摘要： An integrated circuit fabrication process is provided in which a sub-level local interconnect is formed between a gate conductor of one transistor and a junction of another transistor. The formation of a sub-level local interconnect allows for higher packing density by removing the local interconnect to a sub-level dielectrically spaced from possibly other local interconnects and from the distal interconnect normally associated with device interconnection. A semiconductor topography is provided which includes a first transistor laterally spaced from a second transistor, the transistors being arranged upon and within the substrate. An interlevel dielectric is deposited across the semiconductor topography. A portion of the interlevel dielectric is removed to form a trench. The trench is then filled with a conductive material to form a local interconnect extending horizontally above a portion of the first transistor and a portion of the second transistor. Portions of the interlevel dielectric and the local interconnect are removed in sequence while retaining the patterned masking layer. Removal of the local interconnect forms vias extending to the gate conductor of one transistor and to a junction of the other transistor, or from the gate conductor of one transistor to a junction of the same transistor. A conductive material may be deposited in these vias to form plugs therein. Further, a capping dielectric layer may be deposited upon the interlevel dielectric and contact regions may be formed which abut the plugs. Therefore, distal interconnect conductive layers may then be formed dielectrically above the local interconnect which are then electrically coupled to the local interconnect through the contact regions.

摘要翻译： 提供一种集成电路制造工艺，其中在一个晶体管的栅极导体和另一个晶体管的结之间形成子级局部互连。 子级局部互连的形成允许通过将本地互连移除到与可能的其它本地互连以及通常与设备互连相关联的远端互连的介电间隔的子级别来实现更高的堆叠密度。 提供半导体形貌，其包括与第二晶体管横向隔开的第一晶体管，晶体管布置在衬底上和衬底内。 跨越半导体形貌沉积层间电介质。 去除层间电介质的一部分以形成沟槽。 然后用导电材料填充沟槽，以形成在第一晶体管的一部分和第二晶体管的一部分上方水平延伸的局部互连。 层叠电介质和局部互连的部分在保持图案化掩模层的同时被顺序地去除。 去除局部互连形成延伸到一个晶体管的栅极导体和另一个晶体管的结或从一个晶体管的栅极导体到同一晶体管的结的结的通孔。 导电材料可以沉积在这些通孔中以在其中形成插塞。 此外，可以在层间电介质上沉积覆盖电介质层，并且可以形成接触插塞的接触区域。 因此，远端互连导电层然后可以介电地形成在局部互连上方，然后电连接到局部互连通过接触区域。

公开(公告)号：US5943562A

公开(公告)日：1999-08-24

申请号：US949889

申请日：1997-10-14

申请人： Mark I. Gardner ,  Daniel Kadosh ,  Michael P. Duane

发明人： Mark I. Gardner ,  Daniel Kadosh ,  Michael P. Duane

IPC分类号： H01L21/8234 ,  H01L27/092 ,  H01L21/336 ,  H01L21/762

CPC分类号： H01L27/0922 ,  H01L21/823418

摘要： A method is provided for forming a transistor in which the gate is coupled to a second substrate dielectrically spaced above a first substrate. According to an embodiment, a polysilicon layer is formed across an interposing dielectric layer which is disposed across a single crystalline silicon substrate. The polysilicon layer is doped, making it the second semiconductor substrate. Trench isolation structures may be formed within the second substrate between ensuing active areas. A gate oxide is formed across the second substrate, and an opening is etched through the gate oxide down to the second substrate. A conductive material is formed within the opening, and polysilicon is deposited across the gate oxide. The polysilicon may be etched to form a gate conductor above the gate oxide. LDD implant areas are formed within the second substrate between the gate conductor and adjacent isolation structures. Dielectric spacers are formed upon the opposed sidewall surfaces of the gate conductor, and S/D regions are formed within the second substrate. The S/D implant is self-aligned to the exposed lateral edges of the dielectric spacers. The resulting transistor may be switched on quickly and has reduced current leakage in the off state. Transistors formed within and upon the first substrate are isolated from noise which may be induced in the second substrate.

摘要翻译： 提供了一种用于形成晶体管的方法，其中栅极耦合到在第一衬底上介电间隔的第二衬底。 根据一个实施例，跨越设置在单晶硅衬底上的插入介质层跨越形成多晶硅层。 掺杂多晶硅层，使其成为第二半导体衬底。 沟槽隔离结构可以在第二衬底内形成在随后的有效区域之间。 在第二衬底上形成栅极氧化物，并且通过栅极氧化物蚀刻开口到第二衬底。 导电材料形成在开口内，多晶硅沉积在栅极氧化物上。 可以蚀刻多晶硅以在栅极氧化物上方形成栅极导体。 LDD注入区域形成在栅极导体和相邻隔离结构之间的第二衬底内。 电介质间隔物形成在栅极导体的相对的侧壁表面上，并且S / D区形成在第二衬底内。 S / D植入物与介电间隔物的暴露的侧边缘自对准。 所得到的晶体管可以快速接通并且在断开状态下具有减小的电流泄漏。 在第一衬底内和之上形成的晶体管与可能在第二衬底中感应的噪声隔离。

公开(公告)号：US5937301A

公开(公告)日：1999-08-10

申请号：US912839

申请日：1997-08-19

申请人： Mark I. Gardner ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Daniel Kadosh

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49

CPC分类号： H01L29/66575 ,  H01L21/28176 ,  H01L29/4983 ,  H01L29/6659 ,  H01L21/26506 ,  Y10S438/97

摘要： A semiconductor device having improved spacers and a process for fabricating the same is provided. The semiconductor device is formed by forming at least one gate electrode over a substrate and forming a spacer layer over the gate electrode. A nitrogen bearing species is implanted into the spacer layer and portions of the spacer layer are removed, using the implanted nitrogen bearing species as a stop point, in order to form spacers on sidewalls of the gate electrode. Removal of the spacer layer may, for example, be performed using a dry or wet etch process.

摘要翻译： 提供了一种具有改进间隔物的半导体器件及其制造方法。 半导体器件通过在衬底上形成至少一个栅电极并在栅电极上形成间隔层而形成。 将含氮物质注入到间隔层中，并且使用注入的含氮物质作为停止点去除间隔层的部分，以便在栅电极的侧壁上形成间隔物。 间隔层的去除可以例如使用干蚀刻或湿法蚀刻工艺进行。

公开(公告)号：US5872029A

公开(公告)日：1999-02-16

申请号：US744402

申请日：1996-11-07

申请人： Mark I. Gardner ,  Daniel Kadosh

发明人： Mark I. Gardner ,  Daniel Kadosh

IPC分类号： H01L21/822 ,  H01L27/06 ,  H01L21/84

CPC分类号： H01L27/0688 ,  H01L21/8221 ,  H01L2924/0002

摘要： A process is provided for producing active and passive devices on various levels of a semiconductor topography. As such, the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed. The multi-level fabrication process not only adds to the overall circuit density, but does so with emphasis placed on high performance interconnection between devices on separate levels. The interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level. This interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of lower level transistor. Alternatively, the gate conductors can be a single conductive entity. In order to abut the gate conductors together, or form a single gate conductor, the upper level transistor is inverted relative to the lower level transistor. In addition to the inverted, shared gate conductor, the multi-level transistor fabrication process incorporates formation of openings and filling of those openings to produce interconnect to junctions of the upper/lower transistors. Interconnecting the gate conductors of a pair of stacked transistors and connecting specific junctions of those transistors allows formation of a high density inverter circuit hereof.

摘要翻译： 提供了一种用于在半导体形貌的各种水平上产生有源和无源器件的工艺。 因此，本方法可以实现三维装置的形成，以增强形成集成电路的总体密度。 多级制造过程不仅增加了整体电路密度，而且重点放在了在不同级别上的器件之间的高性能互连。 互连配置在一个晶体管电平内的特征之间尽可能短，在另一个晶体管级内的特征。 该互连方案通过在下级晶体管的栅极导体上形成上层晶体管的栅极导体来降低电阻率。 或者，栅极导体可以是单个导电实体。 为了将栅导体邻接在一起或形成单个栅极导体，上层晶体管相对于下层晶体管反相。 除了反向共享栅极导体之外，多级晶体管制造工艺包括形成开口和填充这些开口以产生与上/下晶体管的结的互连。 将一对堆叠晶体管的栅极导体和这些晶体管的连接特定结之间的互连允许形成其中的高密度反相器电路。

公开(公告)号：US5849643A

公开(公告)日：1998-12-15

申请号：US862516

申请日：1997-05-23

申请人： Mark C. Gilmer ,  Mark I. Gardner ,  Daniel Kadosh

发明人： Mark C. Gilmer ,  Mark I. Gardner ,  Daniel Kadosh

IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L21/306

CPC分类号： H01L21/28185 ,  H01L21/28211 ,  H01L29/51 ,  Y10S438/905 ,  Y10S438/906

摘要： A method of growing an oxide film in which the upper surface of a semiconductor substrate is cleaned and the semiconductor substrate is dipped into an acidic solution to remove any native oxide from the upper surface. The substrate is then directly transferred from the acidic solution to an oxidation chamber. The oxidation chamber initially contains an inert ambient maintained at a temperature of less than approximately 500.degree. C. The transfer is accomplished without substantially exposing the substrate to oxygen thereby preventing the formation of a native oxide film on the upper surface of the substrate. Thereafter, a fluorine terminated upper surface is formed on the semiconductor substrate. The temperature within the chamber is then ramped from the first temperature to a second or oxidizing temperature if approximately 700.degree. C. to 850.degree. C. The presence of the fluorine terminated upper surface substantially prevents oxidation of the semiconductor substrate during the temperature ramp. A silicon-oxide film such as silicon dioxide is then grown on the fluorine terminated upper surface of the semiconductor substrate by introducing an oxidizing ambient into the chamber. After the formation or growth of the silicon-oxide, polysilicon is deposited on the silicon oxide film.

摘要翻译： 一种生长氧化膜的方法，其中清洁半导体衬底的上表面并将半导体衬底浸入酸性溶液中以从上表面去除任何天然氧化物。 然后将基底从酸性溶液直接转移到氧化室。 氧化室最初包含保持在小于约500℃的温度的惰性环境。转移完成而基本上不暴露于氧气，从而防止在衬底的上表面上形成自然氧化膜。 此后，在半导体衬底上形成氟端接的上表面。 如果约700℃至850℃，则室内的温度然后从第一温度升高至第二温度或氧化温度。氟端接的上表面的存在基本上防止了温度斜坡期间半导体衬底的氧化。 然后通过将氧化环境引入室中，在半导体衬底的氟封端的上表面上生长二氧化硅等氧化硅膜。 在氧化硅的形成或生长之后，多晶硅沉积在氧化硅膜上。

公开(公告)号：US5783458A

公开(公告)日：1998-07-21

申请号：US720731

申请日：1996-10-01

申请人： Daniel Kadosh ,  Robert Dawson ,  Fred N. Hause

发明人： Daniel Kadosh ,  Robert Dawson ,  Fred N. Hause

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/49 ,  H01L29/78 ,  H01L21/265 ,  H01L21/44

CPC分类号： H01L21/28035 ,  H01L21/28176 ,  H01L29/4916 ,  H01L29/66659 ,  H01L29/7835 ,  H01L29/7836

摘要： Various processes are provided for producing a p-channel and/or n-channel transistor. The present processes are thereby applicable to NMOS, PMOS or CMOS integrated circuits, any of which derive a benefit from having an asymmetrical LDD structure. The asymmetrical structure can be produced on a p-channel or n-channel transistor in various ways. According, the present process employs various techniques to form an asymmetrical transistor. The various techniques employ processing steps which vary depending upon the LDD result desired. First, the LDD implant can be performed only in the drain-side of the channel, or in the drain-side as well as the source-side. Second, the gate conductor sidewall surface adjacent the drain can be made thicker than the sidewall surface adjacent the source. Thickening of the drain-side sidewall spacer can be achieved either by depositing oxide upon a nitride-bearing film, or by growing additional oxide upon an exposed silicon surface having the source-side sidewall protected from growth. Third, the drain-side can be enhanced relative to the source-side by using an LTA implant. There may be numerous other modifications and alternative processing steps, all of which are described herein. Regardless of the sequence chosen, a barrier implant may be employed to prevent deleterious ingress of p-type implant species into the channel region. The present fabrication sequence reduces source-side resistance to enhance drive current-a desirable outcome for high speed circuits.

摘要翻译： 提供了用于产生p沟道和/或n沟道晶体管的各种工艺。 因此，本发明的方法可应用于NMOS，PMOS或CMOS集成电路，其中任何一种从具有不对称的LDD结构中获益。 可以以各种方式在p沟道或n沟道晶体管上产生非对称结构。 据此，本方法采用各种技术形成不对称晶体管。 各种技术采用根据​​所需LDD结果而变化的处理步骤。 首先，LDD注入仅能够在沟道的漏极侧，或者在漏极侧以及源极侧进行。 第二，与漏极相邻的栅极导体侧壁表面可以制成比邻近源极的侧壁表面更厚。 漏极侧壁间隔物的增厚可以通过在氮化物承载膜上沉积氧化物，或通过在具有源极侧壁保护生长的暴露的硅表面上生长另外的氧化物来实现。 第三，可以通过使用LTA植入物相对于源极侧的漏极侧增强。 可以存在许多其它修改和替代的处理步骤，其全部在此描述。 不管选择的顺序如何，可以使用阻挡植入物来防止p型植入物质进入通道区域的有害进入。 本制造顺序降低了源极电阻以增强驱动电流 - 高速电路的期望结果。