公开(公告)号：US06873553B1

公开(公告)日：2005-03-29

申请号：US10812533

申请日：2004-03-30

Applicant: Morteza Cyrus Afghahi ,  Esin Terzioglu ,  Gil Winograd

Inventor： Morteza Cyrus Afghahi ,  Esin Terzioglu ,  Gil Winograd

IPC: G11C11/412 ,  G11C16/04

CPC classification number: G11C11/412

Abstract: An SRAM cell eliminates the p-channel pull-up resistors to decrease its physical size. A tracking circuit generates a control signal used to ensure that the memory state is preserved during the idle state. The control signal controls the wordline voltage during the idle state to vary the leakage through the access transistors to ensure that current into the node through the access device is not exceeded by leakage current out of the output nodes through the storage devices. The tracking circuit control signal can also be used to vary the well to substrate bias voltage of the storage devices to decrease the leakage through the storage devices. The control signal can also be used to bias the supply rail voltage to which the storage devices are directly coupled to decrease the amount of leakage through the storage devices. The tracking circuit comprises a number of half configured memory cells that are placed in a state which mimics the stored state in a normal memory cell that would degrade during the idle state. A differential amplifier detects when the output state of the dummy cells have fallen below a predetermined reference voltage. The differential amplifier generates the control signal at a level required to restore the output state to at or near the reference voltage.

Abstract translation: SRAM单元消除了p沟道上拉电阻以减小其物理尺寸。 跟踪电路产生用于确保在空闲状态期间保持存储器状态的控制信号。 控制信号在空闲状态期间控制字线电压以改变通过存取晶体管的泄漏，以确保通过存储装置的输出节点之外的漏电流不会超过通过接入装置进入节点的电流。 跟踪电路控制信号也可以用于改变存储设备的阱到衬底偏置电压，以减少通过存储设备的泄漏。 控制信号也可以用于偏置存储装置直接耦合到的电源轨电压，以减少通过存储装置的泄漏量。 跟踪电路包括多个半配置的存储器单元，其被置于模拟在空闲状态期间将劣化的正常存储器单元中的存储状态的状态。 差分放大器检测虚拟单元的输出状态何时下降到预定参考电压以下。 差分放大器将输出状态恢复到等于或接近参考电压所需的电平。

公开(公告)号：US06862230B2

公开(公告)日：2005-03-01

申请号：US10177286

申请日：2002-06-21

Applicant: Gil I. Winograd ,  Esin Terzioglu

Inventor： Gil I. Winograd ,  Esin Terzioglu

IPC: G06F13/40 ,  G11C7/18 ,  G11C11/419 ,  G11C29/00 ,  G11C7/00

CPC classification number: G11C29/808 ,  G06F13/4086 ,  G11C7/18 ,  G11C11/41 ,  G11C11/419 ,  G11C29/846 ,  G11C29/848

Abstract: The present invention relates to a system and method adapted to increase memory cell and memory architecture design yield. The present invention includes memory architecture having a decoder and a multi-bank memory. The decoder is adapted to decode addresses. The multi-bank memory interacts with the decoder, wherein the multi-bank memory includes at least one output data bit adapted to complete a word for a failing bank in the multi-bank memory.

Abstract translation: 本发明涉及适于增加存储单元和存储器架构设计产量的系统和方法。 本发明包括具有解码器和多存储体存储器的存储器架构。 解码器适用于解码地址。 所述多存储体存储器与所述解码器交互，其中所述多存储体存储器包括适于完成所述多存储体存储器中的故障库的单词的至少一个输出数据位。

公开(公告)号：US06791367B2

公开(公告)日：2004-09-14

申请号：US10101399

申请日：2002-03-19

Applicant: Esin Terzioglu ,  Gil I. Winograd

Inventor： Esin Terzioglu ,  Gil I. Winograd

IPC: H03K19173

CPC classification number: G11C29/785 ,  G11C7/06 ,  G11C7/18 ,  G11C29/72 ,  G11C2207/002 ,  G11C2207/005 ,  H01L27/10

Abstract: The present invention relates to a system and method for increasing the manufacturing yield of a plurality of memory cells used in cell arrays. A programmable fuse, having both hardware and software elements, is used with the plurality of memory cells to indicate that at least one memory cell is unusable and should be shifted out of operation. The software programmable element includes a programmable register adapted to shift in an appropriate value indicating that at least one of the memory cells is flawed. The hardware element includes a fuse gated with the programmable register. Shifting is indicated either by software programmable fuse or hard fuse. Soft fuse registers may be chained together forming a shift register.

Abstract translation: 本发明涉及用于增加在单元阵列中使用的多个存储单元的制造成品率的系统和方法。 具有硬件和软件元件的可编程保险丝与多个存储器单元一起被使用以指示至少一个存储器单元不可用并且应该被移出而不工作。 软件可编程元件包括可编程寄存器，其适于移位指示至少一个存储器单元有缺陷的适当值。 硬件元件包括一个带可编程寄存器的保险丝。 移位由软件可编程保险丝或硬保险丝指示。 软熔丝寄存器可以链接在一起形成移位寄存器。

公开(公告)号：US06745354B2

公开(公告)日：2004-06-01

申请号：US09776263

申请日：2001-02-02

Applicant: Esin Terzioglu

Inventor： Esin Terzioglu

IPC: G11C2900

CPC classification number: G11C7/06

Abstract: In a memory module having a designated group of memory cells assigned to represent a logical portion of the memory structure, a memory redundancy circuit having a redundant group of memory cells; and a redundancy controller coupled with the designated group and the redundant group. The redundancy controller, which can include a redundancy decoder, assigns the redundant group to the logical portion of the memory structure in response to a preselected memory group condition, e.g., a “FAILED” memory group condition. The redundancy controller also can include selectable switches, for example, fuses, which can encode the preselected memory group condition. The designated group of memory cells and the redundant group of memory cells can be a memory row, a memory column, a preselected portion of a memory module, a selectable portion of a memory module, a memory module, or a combination thereof.

Abstract translation: 在具有分配给表示存储器结构的逻辑部分的指定的存储单元组的存储器模块中，具有冗余组存储器单元的存储器冗余电路; 以及与所指定的组和所述冗余组耦合的冗余控制器。 可以包括冗余解码器的冗余控制器响应于预先选择的存储器组条件（例如，“FAILED”存储器组条件）将冗余组分配给存储器结构的逻辑部分。 冗余控制器还可以包括可选择的开关，例如，可以对预先选择的存储器组条件进行编码的熔丝。 指定组的存储器单元和冗余组的存储器单元可以是存储器行，存储器列，存储器模块的预选部分，存储器模块的可选择部分，存储器模块或其组合。

公开(公告)号：US06646954B2

公开(公告)日：2003-11-11

申请号：US10100757

申请日：2002-03-19

Applicant: Gil I. Winograd ,  Esin Terzioglu ,  Ali Anvar ,  Sami Issa

Inventor： Gil I. Winograd ,  Esin Terzioglu ,  Ali Anvar ,  Sami Issa

IPC: G11C800

CPC classification number: G11C11/419 ,  G06F13/4086 ,  G11C5/025 ,  G11C5/06 ,  G11C7/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C29/808 ,  G11C29/848

Abstract: The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. The local sense amplifier interfaces with at least the decoder and cell array, and is adapted to precharge and equalize at least one line coupled thereto. The local controller interfaces with and coordinates the activities of at least the local decoder and sense amplifier.

Abstract translation: 本发明涉及同步自定时存储装置。 该装置包括形成单元阵列的多个存储单元，与单元阵列接口的至少一个本地解码器，至少一个本地读出放大器和至少一个本地控制器。 本地感测放大器至少与解码器和单元阵列接口，并且适于对与其耦合的至少一条线进行预充电和均衡。 本地控制器与至少本地解码器和读出放大器的活动接口并进行协调。

公开(公告)号：US06414899B2

公开(公告)日：2002-07-02

申请号：US09775478

申请日：2001-02-02

Applicant: Morteza Cyrus Afghahi ,  Esin Terzioglu

Inventor： Morteza Cyrus Afghahi ,  Esin Terzioglu

IPC: G11C800

CPC classification number: G11C7/06

Abstract: A limited swing driver with a pass transistor coupled between a memory cell and an associated bitline; an inverter, its output coupled to the gate of the pass transistor, and its input coupled with the memory cell. A memory node is formed at the juncture of the inverter input and the memory cell forming a memory node. The driver also includes a discharge transistor coupled between the memory node and ground. The discharge transistor is driven by an input on the discharge transistor gate. It is preferred that the discharge transistor being programmed to produce a limited swing voltage at the memory node. It is desirable that the limited swing voltage be less than about 350 mV, and it is preferable that the limited swing voltage be between about 300 mV and about 200 mV. In addition, the limited swing voltage driver can include a tri-state output enable isolating the memory node from the bitline, particularly if the bitline is a shared or multiplexed bitline; and a self-reset circuit resetting the driver to a predetermined signal state.

Abstract translation: 具有耦合在存储器单元和相关位线之间的传输晶体管的限制摆动驱动器; 反相器，其输出耦合到传输晶体管的栅极，其输入端与存储单元耦合。 存储器节点形成在逆变器输入端和形成存储器节点的存储单元的接合处。 驱动器还包括耦合在存储器节点和地之间的放电晶体管。 放电晶体管由放电晶体管栅极上的输入驱动。 优选地，放电晶体管被编程以在存储器节点处产生有限的摆动电压。 希望有限的摆动电压小于约350mV，并且优选地，限制摆动电压在约300mV与约200mV之间。 此外，有限摆幅电压驱动器可以包括三位输出使得能够将存储器节点与位线隔离，特别是如果位线是共享或多路复用的位线; 以及将所述驱动器复位到预定信号状态的自复位电路。

公开(公告)号：US20130208556A1

公开(公告)日：2013-08-15

申请号：US13460862

申请日：2012-05-01

Applicant: Esin Terzioglu ,  Balachander Ganesan ,  Alex Dongkyu Park ,  Sei Seung Yoon

Inventor： Esin Terzioglu ,  Balachander Ganesan ,  Alex Dongkyu Park ,  Sei Seung Yoon

IPC: G11C8/10

CPC classification number: G11C8/10 ,  G11C7/20

Abstract: Power-on-reset (POR) circuits for resetting memory devices, and related circuits, systems, and methods are disclosed. In one embodiment, a POR circuit is provided. The POR circuit is configured to receive as input, a plurality of decoded address outputs from at least one memory decoding device. The POR circuit is further configured to generate a POR reset if any of the plurality of decoded address outputs are active. As a result, memory decoding device latches can be reset to a known, default condition to avoid causing an unintentional word line selection in the memory during power-on state before an external reset is available. Because the POR circuit can generate the POR reset without need of an external reset, the memory decoding devices can be reset quickly to allow for quicker availability of memory after a power-on condition.

Abstract translation: 公开了用于重置存储器件的上电复位（POR）电路以及相关电路，系统和方法。 在一个实施例中，提供了一个POR电路。 POR电路被配置为从至少一个存储器解码装置接收多个解码的地址输出作为输入。 POR电路还被配置为如果多个解码的地址输出中的任一个是有效的，则产生POR复位。 结果，存储器解码装置锁存器可以被重置为已知的默认条件，以避免在外部复位可用之前在上电状态期间在存储器中引起无意的字线选择。 由于POR电路可以在不需要外部复位的情况下生成POR复位，所以可以快速复位存储器解码器件，以便在上电状态后可以更快地提供存储器的可用性。

公开(公告)号：US20120185664A1

公开(公告)日：2012-07-19

申请号：US13435020

申请日：2012-03-30

Applicant: Ali Anvar ,  Gil I. Winograd ,  Esin Terzioglu

Inventor： Ali Anvar ,  Gil I. Winograd ,  Esin Terzioglu

IPC: G06F12/00

CPC classification number: G11C11/419 ,  G06F13/4086 ,  G11C5/025 ,  G11C5/06 ,  G11C7/06 ,  G11C7/1039 ,  G11C7/1072 ,  G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/10 ,  G11C8/12 ,  G11C8/14 ,  G11C11/41 ,  G11C11/412 ,  G11C11/413 ,  G11C29/808 ,  G11C29/848

Abstract: The present invention relates to a system and method for adjusting timing of memory access operations to a memory block. In one embodiment, a controller may be in communication with a memory block. The controller may be adapted to adjust timing of a memory access operation to the memory block by extending a portion of a clock pulse to compensate for delay associated with the memory block. The delay may correspond to a predecoder delay or a global decoder delay. The clock pulse may be a read clock pulse or a write clock pulse. In one embodiment, the controller may be adapted to adjust timing of a read clock pulse differently from a write clock pulse

Abstract translation: 本发明涉及一种用于调整对存储器块的存储器访问操作的定时的系统和方法。 在一个实施例中，控制器可以与存储器块通信。 控制器可以适于通过延长时钟脉冲的一部分来补偿与存储器块相关联的延迟来调整对存储器块的存储器访问操作的定时。 延迟可以对应于预解码器延迟或全局解码器延迟。 时钟脉冲可以是读时钟脉冲或写时钟脉冲。 在一个实施例中，控制器可以适于调整与写入时钟脉冲不同的读取时钟脉冲的定时

公开(公告)号：US20110317468A1

公开(公告)日：2011-12-29

申请号：US12849862

申请日：2010-08-04

Applicant: Esin Terzioglu

Inventor： Esin Terzioglu

IPC: G11C17/16 ,  G11C17/00

CPC classification number: G11C17/16 ,  G11C17/18

Abstract: Read and write operations of a non-volatile memory (NVM) bitcell have different optimum parameters resulting in a conflict during design of the NVM bitcell. A single bitline in the NVM bitcell prevents optimum read performance. Read performance may be improved by splitting the read path and the write path in a NVM bitcell between two bitlines. A read bitline of the NVM bitcell has a low capacitance for improved read operation speed and decreased power consumption. A write bitline of the NVM bitcell has a low resistance to handle large currents present during write operations. A memory element of the NVM bitcell may be a fuse, anti-fuse, eFUSE, or magnetic tunnel junction. Read performance may be further enhanced with differential sensing read operations.

Abstract translation: 非易失性存储器（NVM）位单元的读写操作具有不同的最佳参数，从而在NVM位单元的设计过程中产生冲突。 NVM位单元中的单个位线阻止了最佳的读取性能。 通过将读路径和写入路径分割在两个位线之间的NVM位单元中可以提高读取性能。 NVM位单元的读取位线具有低电容，从而提高读取操作速度并降低功耗。 NVM位单元的写位线具有低电阻以处理写操作期间存在的大电流。 NVM位单元的存储元件可以是保险丝，反熔丝，eFUSE或磁性隧道结。 差分感测读取操作可以进一步增强读取性能。

公开(公告)号：US07768813B2

公开(公告)日：2010-08-03

申请号：US11845327

申请日：2007-08-27

Applicant: Esin Terzioglu ,  Melinda L. Miller

Inventor： Esin Terzioglu ,  Melinda L. Miller

IPC: G11C11/24

CPC classification number: G11C7/12 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1069 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028

Abstract: In one embodiment, a DRAM is provided that includes: a word line intersecting with a pair of bit lines, the DRAM including a memory cell at each intersection, each memory cell including an access transistor adapted to couple a storage cell to the corresponding bit line if its gate voltage is raised; and a word line compensation circuit adapted to compensate for a capacitively-coupled voltage increase on the corresponding bit line if the access transistor's gate voltage is raised.

Abstract translation: 在一个实施例中，提供了DRAM，其包括：与一对位线相交的字线，所述DRAM包括在每个交叉点处的存储单元，每个存储单元包括适于将存储单元耦合到相应位线的存取晶体管 如果其栅极电压升高; 以及字线补偿电路，其适于在存取晶体管的栅极电压升高时补偿对应位线上的电容耦合电压增加。