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    Integrated chemical microreactor with separated channels
    52.
    发明申请
    Integrated chemical microreactor with separated channels 有权
    具有分离通道的集成化学微反应器

    公开(公告)号：US20050142597A1

    公开(公告)日：2005-06-30

    申请号：US10997235

    申请日：2004-11-24

    申请人： Ubaldo Mastromatteo ,  Flavio Villa ,  Gabriele Barlocchi

    发明人： Ubaldo Mastromatteo ,  Flavio Villa ,  Gabriele Barlocchi

    IPC分类号： B01L3/00 ,  B01L7/00 ,  B81B3/00 ,  C12M1/34 ,  C12Q1/68 ,  H01L21/00

    CPC分类号： B01L3/502715 ,  B01L3/5025 ,  B01L3/502707 ,  B01L7/52 ,  B01L2200/027 ,  B01L2200/12 ,  B01L2300/044 ,  B01L2300/0816 ,  B01L2300/1827

    摘要： The microreactor is formed by a sandwich including a first body, an intermediate sealing layer and a second body. A buried channel extends in the first body and communicates with the surface of the first body through a first and a second apertures. A first and a second reservoirs are formed in the second body and are at least partially aligned with the first and second apertures. The sealing layer separates the first aperture from the first reservoir and the second aperture from the second reservoir, thereby avoiding contamination of liquids contained in the buried channel from the outside and from any adjacent buried channels. The sealing layer is perforated during use of the device, but a resilient plug can be used to reseal the device.

    摘要翻译： 微反应器由包括第一主体，中间密封层和第二主体的夹层形成。 掩埋通道在第一主体中延伸并且通过第一和第二孔与第一主体的表面连通。 第一和第二储存器形成在第二主体中并且至少部分地与第一和第二孔对准。 密封层将第一孔与第一储存器和第二孔分隔开来自第二储存器，从而避免了从外部和任何相邻的埋入通道污染包含在掩埋通道中的液体。 在使用该装置期间密封层是穿孔的，但是可以使用弹性塞来重新密封装置。

    Quantitative assessment of the geometrical distortion suffered by the profile of a semiconductor wafer
    53.
    发明授权
    Quantitative assessment of the geometrical distortion suffered by the profile of a semiconductor wafer 失效
    由半导体滤波器轮廓引起的几何失真的定量评估

    公开(公告)号：US5152168A

    公开(公告)日：1992-10-06

    申请号：US631018

    申请日：1990-12-21

    申请人： Gabriele Barlocchi ,  Fabrizio Ghironi

    发明人： Gabriele Barlocchi ,  Fabrizio Ghironi

    IPC分类号： G01B7/28 ,  H01L21/66 ,  H01L21/68

    CPC分类号： H01L21/681 ,  G01B7/28 ,  H01L22/12

    摘要： A method for the quantitative assessment of the degree of geometrical deformation undergone by a surface profile of a wafer following the formation of a conformal surface layer employs a simple mechanical profilometer, whose stylus is run over a target morphological detail comprising at least two mutually parallel ridges or reliefs which rise above the plane of the surface of the wafer for a height of between 0.1 and 0.5 .mu.m, and which enclose between them a depression of a width of between 2 and 4 .mu.m, in order to determine the elevation of the bottom of the valley between the two ridges relative to the plane of the surface of the wafer from which the ridges rise following the formation of one or more similar surface layers. The vertical measurement of the elevation undergone by the bottom of the valley in itself represents a quantitative index of the vertical and horizontal geometrical deformation undergone by the details of the surface profile of the wafer. In order to determine characteristics of automatic alignability by a particular apparatus employing said target details for automatic alignment, it is possible to establish a maximum value for said distortion index, determined as above, above which the automatic alignment capability is lost.

    Method for forming horizontal buried channels or cavities in wafers of monocrystalline semiconductor material
    54.
    发明授权
    Method for forming horizontal buried channels or cavities in wafers of monocrystalline semiconductor material 有权
    在单晶半导体材料的晶片中形成水平埋入通道或空腔的方法

    公开(公告)号：US07705416B2

    公开(公告)日：2010-04-27

    申请号：US10667113

    申请日：2003-09-18

    申请人： Gabriele Barlocchi ,  Flavio Villa

    发明人： Gabriele Barlocchi ,  Flavio Villa

    IPC分类号： H01L29/00

    CPC分类号： H01L21/2007 ,  H01L21/30608 ,  H01L21/3086 ,  H01L21/76251 ,  H01L21/76262 ,  H01L21/764

    摘要： A method of forming buried cavities in a wafer of monocrystalline semiconductor material with at least one cavity formed in a substrate of monocrystalline semiconductor material by timed TMAH etching silicon; covering the cavity with a material inhibiting epitaxial growth; and growing a monocrystalline epitaxial layer above the substrate and the cavities. Thereby, the cavity is completely surrounded by monocrystalline material. Starting from this wafer, it is possible to form a thin membrane. The original wafer must have a plurality of elongate cavities or channels, parallel and adjacent to one another. Trenches are then excavated in the epitaxial layer as far as the channels, and the dividers between the channels are removed by timed TMAH etching.

    摘要翻译： 在单晶半导体材料的晶片中形成掩埋空穴的方法，其中至少一个腔通过定时的TMAH蚀刻硅在单晶半导体材料的衬底中形成; 用抑制外延生长的材料覆盖空腔; 以及在衬底和空腔上生长单晶外延层。 因此，腔体被单晶材料完全包围。 从该晶片开始，可以形成薄膜。 原始晶片必须具有彼此平行并相邻的多个细长空腔或通道。 然后在外延层中挖沟直到沟道，并且通过定时TMAH蚀刻去除沟道之间的分隔线。

    Inexpensive method of manufacturing an SOI wafer
    58.
    发明授权
    Inexpensive method of manufacturing an SOI wafer 有权
    制造SOI晶片的廉价方法

    公开(公告)号：US06350657B1

    公开(公告)日：2002-02-26

    申请号：US09359870

    申请日：1999-07-26

    申请人： Ubaldo Mastromatteo ,  Flavio Villa ,  Gabriele Barlocchi

    发明人： Ubaldo Mastromatteo ,  Flavio Villa ,  Gabriele Barlocchi

    IPC分类号： H01L21311

    CPC分类号： H01L21/3065 ,  H01L21/7624 ,  H01L21/76262

    摘要： A method of manufacturing an SOI (silicon on insulator) wafer includes the step of selective anisotropic etching to form, in the substrate, trenches which extend to a predetermined depth from a major surface of the substrate and between which pillar portions of the substrate are defined. The method further includes the step of selective isotropic etching to enlarge the trenches, starting at a predetermined distance from the major surface, thus reducing the thicknesses of the pillar portions of the substrate between adjacent trenches. Also, the method includes the steps of selective oxidation to convert the pillar portions of reduced thickness of the substrate into silicon dioxide and to fill the trenches with silicon dioxide, starting substantially from the predetermined distance, and epitaxial growth of a silicon layer on the major surface of the substrate. The method permits more freedom in the selection of the dimensional ratios between the trenches and the pillars and thus enables the necessary crystallographic quality of the epitaxial layer to be achieved, ensuring a continuous buried oxide layer.

    摘要翻译： 制造SOI（绝缘体上硅）晶片的方法包括选择性各向异性蚀刻的步骤，以在衬底中形成从衬底的主表面延伸到预定深度并且在衬底的哪个柱部分被限定的沟槽之间 。 该方法还包括选择性各向同性蚀刻步骤，以从主表面预定距离开始扩大沟槽，从而减小相邻沟槽之间的衬底的柱部分的厚度。 此外，该方法包括以下步骤：选择性氧化以将衬底的厚度的柱部分转换为二氧化硅，并且以基本上从预定距离开始的二氧化硅填充沟槽，以及主层上的硅层的外延生长 基板的表面。 该方法允许在选择沟槽和柱之间的尺寸比例时更多的自由度，并且因此能够实现外延层的必要的晶体学质量，确保连续的掩埋氧化物层。

    Process for manufacturing wafers of semiconductor material by layer transfer
    59.
    发明申请
    Process for manufacturing wafers of semiconductor material by layer transfer 有权
    通过层转移制造半导体材料的晶片的工艺

    公开(公告)号：US20060063352A1

    公开(公告)日：2006-03-23

    申请号：US11225883

    申请日：2005-09-13

    申请人： Gabriele Barlocchi ,  Flavio Villa

    发明人： Gabriele Barlocchi ,  Flavio Villa

    IPC分类号： H01L21/30 ,  H01L21/20

    CPC分类号： H01L21/3247 ,  H01L21/3043 ,  H01L21/76251 ,  H01L21/76259

    摘要： A process manufactures a wafer using semiconductor processing techniques. A bonding layer is formed on a top surface of a first wafer; a deep trench is dug in a substrate of semiconductor material belonging to a second wafer. A top layer of semiconductor material is formed on top of the substrate so as to close the deep trench at the top and form at least one buried cavity. The top layer of the second wafer is bonded to the first wafer through the bonding layer. The two wafers are subjected to a thermal treatment that causes bonding of at least one portion of the top layer to the first wafer and widening of the buried cavity. In this way, the portion of the top layer bonded to the first wafer is separated from the rest of the second wafer, to form a composite wafer.

    摘要翻译： 一种工艺使用半导体处理技术制造晶片。 在第一晶片的顶表面上形成接合层; 在属于第二晶片的半导体材料的衬底中挖出深沟槽。 半导体材料的顶层形成在衬底的顶部上，以封闭顶部的深沟槽并形成至少一个埋入空腔。 第二晶片的顶层通过结合层结合到第一晶片。 对这两个晶片进行热处理，其导致顶层的至少一部分与第一晶片的接合和掩埋腔的加宽。 以这种方式，将结合到第一晶片的顶层的部分与第二晶片的其余部分分离，以形成复合晶片。