公开(公告)号：US08373208B2

公开(公告)日：2013-02-12

申请号：US12799810

申请日：2010-04-30

申请人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

发明人： Madhur Bobde ,  Lingpeng Guan ,  Anup Bhalla ,  Hamza Yilmaz

IPC分类号： H01L21/8232

CPC分类号： H01L29/808 ,  H01L29/0626 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0843 ,  H01L29/0878 ,  H01L29/0882 ,  H01L29/1066 ,  H01L29/1095 ,  H01L29/4175 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/66696 ,  H01L29/66901 ,  H01L29/7817 ,  H01L29/7821

摘要： A lateral super junction JFET is formed from stacked alternating P type and N type semiconductor layers over a P-epi layer supported on an N+ substrate. An N+ drain column extends down through the super junction structure and the P-epi to connect to the N+ substrate to make the device a bottom drain device. N+ source column and P+ gate column extend through the super junction but stop at the P-epi layer. A gate-drain avalanche clamp diode is formed from the bottom the P+ gate column through the P-epi to the N+ drain substrate.

摘要翻译： 横向超结JFET由负载在N +衬底上的P表面层上的堆叠的交替P型和N型半导体层形成。 N +漏极柱向下延伸穿过超结结构和P-epi以连接到N +衬底以使器件成为底部漏极器件。 N +源极柱和P +栅极柱延伸穿过超级结，但在P-epi层处停止。 栅极 - 漏极雪崩钳位二极管从P +栅极底部通过P-epi到N +漏极衬底形成。

公开(公告)号：US08362547B2

公开(公告)日：2013-01-29

申请号：US12005166

申请日：2007-12-21

申请人： Anup Bhalla ,  Xiaobin Wang ,  Ji Pan ,  Sung-Po Wei

发明人： Anup Bhalla ,  Xiaobin Wang ,  Ji Pan ,  Sung-Po Wei

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7811 ,  H01L21/26513 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66143 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7809 ,  H01L29/7813 ,  H01L29/8725

摘要： A semiconductor device formed on a semiconductor substrate includes: an epitaxial layer overlaying the semiconductor substrate; a drain formed on back of the semiconductor substrate; a drain region that extends into the epitaxial layer; and an active region. The active region includes: a body disposed in the epitaxial layer, having a body top surface; a source embedded in the body, extending from the body top surface into the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; an active region contact trench extending through the source and the body into the drain region; an active region contact electrode disposed within the active region contact trench, wherein the active region contact electrode and the drain region form a Schottky diode; and a Schottky barrier controlling layer.

摘要翻译： 形成在半导体衬底上的半导体器件包括：覆盖半导体衬底的外延层; 在半导体衬底背面形成的漏极; 漏极区域，其延伸到所述外延层中; 和活跃区域。 有源区包括：设置在外延层中的具有主体顶表面的主体; 嵌入在体内的源体，从身体顶面延伸到体内; 延伸到外延层中的栅极沟槽; 设置在栅极沟槽中的栅极; 有源区域接触沟槽，其延伸穿过所述源极和所述本体进入所述漏极区域; 有源区接触电极，设置在有源区接触沟槽内，其中有源区接触电极和漏区形成肖特基二极管; 和肖特基势垒控制层。

公开(公告)号：US20130001694A1

公开(公告)日：2013-01-03

申请号：US13170965

申请日：2011-06-28

申请人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Jun Hu ,  Wayne F. Eng

发明人： Lingpeng Guan ,  Madhur Bobde ,  Anup Bhalla ,  Jun Hu ,  Wayne F. Eng

IPC分类号： H01L23/60 ,  H01L21/336

CPC分类号： H01L29/66113 ,  H01L21/265 ,  H01L21/76224 ,  H01L21/822 ,  H01L27/0248 ,  H01L27/0255

摘要： A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.

摘要翻译： 具有降低的钳位电压的低电容瞬态电压抑制器包括n +型衬底，衬底上的第一外延层，形成在第一外延层内的掩埋层，在第一外延层上形成的第二外延层，以及在第一外延层上形成的注入层 掩埋层下面的第一个外延层。 植入层延伸超过掩埋层。 第一沟槽位于掩埋层的边缘和植入层的边缘。 第二沟槽位于掩埋层的另一边缘并延伸到植入层中。 第三沟槽位于植入层的另一边缘。 每个沟槽衬有介电层。 一组源区形成在第二外延层的顶表面内。 沟渠和源区交替出现。 在第二外延层中形成一对注入区。

公开(公告)号：US20120329225A1

公开(公告)日：2012-12-27

申请号：US13604286

申请日：2012-09-05

申请人： Anup Bhalla ,  Sik Lui ,  Tiesheng Li

发明人： Anup Bhalla ,  Sik Lui ,  Tiesheng Li

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811

摘要： Fabricating a semiconductor device includes forming a mask on a substrate having a top substrate surface; forming a gate trench in the substrate, through the mask; depositing gate material in the gate trench; removing the mask to leave a gate structure; implanting a body region; implanting a source region; forming a source body contact trench having a trench wall and a trench bottom; forming a plug in the source body contact trench, wherein the plug extends below a bottom of the body region; and disposing conductive material in the source body contact trench, on top of the plug.

摘要翻译： 制造半导体器件包括在具有顶部衬底表面的衬底上形成掩模; 通过掩模在衬底中形成栅极沟槽; 在栅极沟槽中沉积栅极材料; 取下面罩离开门结构; 植入人体区域; 植入源区; 形成具有沟槽壁和沟槽底部的源体接触沟槽; 在源体接触沟槽中形成插塞，其中插头延伸到身体区域的底部下方; 并且在所述源体接触沟槽中，在所述插头的顶部上设置导电材料。

公开(公告)号：US20120319132A1

公开(公告)日：2012-12-20

申请号：US13162407

申请日：2011-06-16

申请人： Anup Bhalla ,  Madhur Bobde ,  Lingpeng Guan

发明人： Anup Bhalla ,  Madhur Bobde ,  Lingpeng Guan

IPC分类号： H01L27/088 ,  H01L21/8234

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/456 ,  H01L29/47 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7806

摘要： An integrated structure includes a plurality of split-gate trench MOSFETs. A plurality of trenches is formed within the silicon carbide substrate composition, each trench is lined with a passivation layer, each trench being substantially filled with a first conductive region a second conductive region and an insulating material having a dielectric constant similar to a dielectric constant of the silicon carbide substrate composition. The first conductive region is separated from the passivation layer by the insulating material. The first and second conductive regions form gate regions for each trench MOSFET. The first conductive region is separated from the second conductive region by the passivation layer. A doped body region of a first conductivity type formed at an upper portion of the substrate composition and a doped source region of a second conductivity type formed inside the doped body region.

摘要翻译： 集成结构包括多个分离栅沟槽MOSFET。 在碳化硅衬底组合物中形成多个沟槽，每个沟槽衬有钝化层，每个沟槽基本上填充有第一导电区域，第二导电区域和绝缘材料，其介电常数类似于介电常数 碳化硅衬底组合物。 第一导电区域通过绝缘材料与钝化层分离。 第一和第二导电区域形成每个沟槽MOSFET的栅极区域。 第一导电区域通过钝化层与第二导电区域分离。 在衬底组合物的上部形成的第一导电类型的掺杂体区域和形成在掺杂体区域内的第二导电类型的掺杂源区。

公开(公告)号：US20120306043A1

公开(公告)日：2012-12-06

申请号：US13534854

申请日：2012-06-27

申请人： Ji Pan ,  Anup Bhalla

发明人： Ji Pan ,  Anup Bhalla

IPC分类号： H01L29/47

CPC分类号： H01L29/66727 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/782

摘要： A Schottky diode includes a Schottky barrier and a plurality of dopant regions disposed near the Schottky barrier as floating islands to function as PN junctions for preventing a leakage current generated from a reverse voltage. At least a trench opened in a semiconductor substrate with a Schottky barrier material disposed therein constitutes the Schottky barrier. The Schottky barrier material may also be disposed on sidewalls of the trench for constituting the Schottky barrier. The trench may be filled with the Schottky barrier material composed of Ti/TiN or a tungsten metal disposed therein for constituting the Schottky barrier. The trench is opened in a N-type semiconductor substrate and the dopant regions includes P-doped regions disposed under the trench constitute the floating islands. The P-doped floating islands may be formed as vertical arrays under the bottom of the trench.

摘要翻译： 肖特基二极管包括肖特基势垒和设置在肖特基势垒附近的多个掺杂区，作为浮岛，用作用于防止从反向电压产生的漏电流的PN结。 在其中设置有肖特基势垒材料的半导体衬底中开放的至少一个沟槽构成肖特基势垒。 肖特基势垒材料也可以设置在用于构成肖特基势垒的沟槽的侧壁上。 沟槽可以填充由设置在其中的用于构成肖特基势垒的Ti / TiN或其中的钨金属组成的肖特基势垒材料。 沟槽在N型半导体衬底中打开，并且掺杂区包括设置在沟槽下方的P掺杂区构成浮岛。 P掺杂的浮岛可以在沟槽底部形成为垂直阵列。

公开(公告)号：US20120104555A1

公开(公告)日：2012-05-03

申请号：US12925869

申请日：2010-10-31

申请人： Madhur Bobde ,  Anup Bhalla

发明人： Madhur Bobde ,  Anup Bhalla

IPC分类号： H01L29/739 ,  H01L21/331

CPC分类号： H01L29/7397 ,  H01L29/0696 ,  H01L29/402 ,  H01L29/66348

摘要： This invention discloses an insulated gate bipolar transistor (IGBT) device formed in a semiconductor substrate. The IGBT device has a split-shielded trench gate that includes an upper gate segment and a lower shield segment. The IGBT device may further include a dummy trench filled with a dielectric layer disposed at a distance away from the split-shielded trench gate. The IGBT device further includes a body region extended between the split-shielded trench gate and the dummy trench encompassing a source region surrounding the split-shielded trench gate near a top surface of the semiconductor substrate. The IGBT device further includes a heavily doped N region disposed below the body region and above a source-dopant drift region above a bottom body-dopant collector region at a bottom surface of the semiconductor substrate. In an alternative embodiment, the IGBT may include a planar gate with a trench shield electrode.

摘要翻译： 本发明公开了一种形成在半导体衬底中的绝缘栅双极晶体管（IGBT）器件。 IGBT器件具有分裂屏蔽沟槽栅极，其包括上栅极段和下屏蔽段。 IGBT器件还可以包括填充有离开分屏蔽沟槽栅极一定距离设置的电介质层的虚拟沟槽。 IGBT器件还包括在分屏蔽沟槽栅极和虚拟沟槽之间延伸的体区，其围绕半导体衬底的顶表面附近的分离屏蔽沟槽栅极的源极区域。 所述IGBT器件还包括设置在所述体区域的下方且位于所述半导体衬底的底表面的底体 - 掺杂剂集电极区域上方的源 - 掺杂剂漂移区上方的重掺杂N区域。 在替代实施例中，IGBT可以包括具有沟槽屏蔽电极的平面栅极。

公开(公告)号：US08110869B2

公开(公告)日：2012-02-07

申请号：US11906476

申请日：2007-10-01

申请人： Anup Bhalla

发明人： Anup Bhalla

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7813 ,  H01L29/872 ,  H01L29/8725

摘要： A semiconductor power device supported on a semiconductor substrate of a first conductivity type with a bottom layer functioning as a bottom electrode and an epitaxial layer overlying the bottom layer with a same conductivity type as the bottom layer. The semiconductor power device includes a plurality of FET cells and each cell further includes a body region of a second conductivity type extending from a top surface into the epitaxial layer. The body region encompasses a heavy body dopant region of second conductivity type. An insulated gate is disposed on the top surface of the epitaxial layer, overlapping a first portion of the body region. A barrier control layer is disposed on the top surface of the epitaxial layer next to the body region away from the insulated gate. A conductive layer overlies the top surface of the epitaxial layer covering a second portion of the body region and the heavy body dopant region extending over the barrier control layer forming a Schottky junction diode.

摘要翻译： 一种半导体功率器件，其被支撑在第一导电类型的半导体衬底上，底层用作底部电极，外延层覆盖在与底层相同的导电类型的底层上。 半导体功率器件包括多个FET单元，并且每个单元还包括从顶表面延伸到外延层中的第二导电类型的体区。 身体区域包括第二导电类型的重体掺杂区域。 绝缘栅极设置在外延层的顶表面上，与身体区域的第一部分重叠。 屏障控制层设置在远离绝缘栅极的身体区域旁边的外延层的顶表面上。 覆盖覆盖主体区域的第二部分的外延层的顶表面上的导电层和在形成肖特基结二极管的势垒控制层上延伸的重体掺杂区域。

公开(公告)号：US08105895B2

公开(公告)日：2012-01-31

申请号：US12932163

申请日：2011-02-17

申请人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

发明人： Anup Bhalla ,  Xiaobin Wang ,  Moses Ho

IPC分类号： H01L21/8234

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/1095 ,  H01L29/456 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/872

摘要： This invention discloses a semiconductor power device that includes an active cell area having a plurality of power transistor cells. Each of said power transistor cells has a planar Schottky diode that includes a Schottky junction barrier metal covering areas above gaps between separated body regions between two adjacent power transistor cells. The separated body regions further provide a function of adjusting a leakage current of said Schottky diode in each of said power transistor cells. Each of the planar Schottky diodes further includes a Shannon implant region disposed in a gap between the separated body regions of two adjacent power transistor cells for further adjusting a leakage current of said Schottky diode. Each of the power transistor cells further includes heavy body doped regions in the separated body regions next to source regions surrounding said Schottky diode forming a junction barrier Schottky (JBS) pocket region.

摘要翻译： 本发明公开了一种包括具有多个功率晶体管单元的有源单元区域的半导体功率器件。 每个所述功率晶体管单元具有平面肖特基二极管，其包括覆盖两个相邻功率晶体管单元之间的分离体区域之间的间隙上方的区域的肖特基结阻挡金属。 分离体区域还提供调节每个所述功率晶体管单元中的所述肖特基二极管的漏电流的功能。 每个平面肖特基二极管还包括设置在两个相邻功率晶体管单元的分离的体区之间的间隙中的香农注入区，用于进一步调整所述肖特基二极管的漏电流。 每个功率晶体管单元进一步包括分离体区域中的重体掺杂区域，其邻近形成结屏障肖特基（JBS）口袋区域的围绕所述肖特基二极管的源极区域。

公开(公告)号：US08093651B2

公开(公告)日：2012-01-10

申请号：US12005146

申请日：2007-12-21

申请人： Anup Bhalla ,  Xiaobin Wang ,  Ji Pan ,  Sung-Po Wei

发明人： Anup Bhalla ,  Xiaobin Wang ,  Ji Pan ,  Sung-Po Wei

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66484 ,  H01L21/26586 ,  H01L29/0623 ,  H01L29/1095 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/456 ,  H01L29/47 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813

摘要： A semiconductor device is formed on a semiconductor substrate. The device comprises a drain, an epitaxial layer overlaying the drain, and an active region. The active region comprises a body disposed in the epitaxial layer, having a body top surface and a body bottom surface, a source embedded in the body, extending from the body top surface into the body, a gate trench extending into the epitaxial layer, a gate disposed in the gate trench, an active region contact trench extending through the source and at least part of the body into the drain, wherein the active region contact trench is shallower than the body bottom surface, and an active region contact electrode disposed within the active region contact trench.

摘要翻译： 半导体器件形成在半导体衬底上。 该器件包括漏极，覆盖漏极的外延层和有源区。 有源区域包括设置在外延层中的主体，具有主体顶表面和主体底表面，嵌入在主体中的源，从主体顶表面延伸到主体中，延伸到外延层中的栅沟槽， 设置在所述栅极沟槽中的栅极，延伸穿过所述源极和所述主体的至少一部分进入所述漏极的有源区接触沟槽，其中所述有源区接触沟槽比所述主体底表面浅，以及设置在所述栅极沟槽内的有源区接触电极 有源区接触沟槽。