Semiconductor Device Comprising a Capacitor in the Metallization System Formed by a Hard Mask Patterning Regime
    56.
    发明申请
    Semiconductor Device Comprising a Capacitor in the Metallization System Formed by a Hard Mask Patterning Regime 审中-公开
    包括由硬掩模图案形成的金属化系统中的电容器的半导体器件

    公开(公告)号:US20110241167A1

    公开(公告)日:2011-10-06

    申请号:US12942664

    申请日:2010-11-09

    摘要: Capacitors may be formed in the metallization system of semiconductor devices without requiring a modification of the hard mask patterning process for forming vias and trenches in the dielectric material of the metallization layer under consideration. To this end, a capacitor opening is formed prior to actually forming the hard mask for patterning the trench and via openings, wherein the hard mask material may thus preserve integrity of the capacitor opening and may remain as a portion of the electrode material after filling in the conductive material for the metal lines, vias and the capacitor electrode.

    摘要翻译: 可以在半导体器件的金属化系统中形成电容器,而不需要修改用于在考虑的金属化层的电介质材料中形成通路和沟槽的硬掩模图案化工艺。 为此,在实际形成用于图案化沟槽和通孔开口的硬掩模之前形成电容器开口,其中硬掩模材料因此可以保持电容器开口的完整性,并且可以在填充之后保留为电极材料的一部分 用于金属线,通孔和电容器电极的导电材料。

    Fabricating vias of different size of a semiconductor device by splitting the via patterning process
    59.
    发明授权
    Fabricating vias of different size of a semiconductor device by splitting the via patterning process 有权
    通过分割通孔图案化工艺制造不同尺寸的半导体器件的通孔

    公开(公告)号:US07977237B2

    公开(公告)日:2011-07-12

    申请号:US12894648

    申请日:2010-09-30

    IPC分类号: H01L21/4763 H01L21/44

    摘要: When forming a complex metallization system in which vias of different lateral size have to be provided, a split patterning sequence may be applied. For this purpose, a lithography process may be specifically designed for the critical via openings and a subsequent second patterning process may be applied for forming the vias of increased lateral dimensions, while the critical vias are masked. In this manner, superior process conditions may be established for each of the patterning sequences.

    摘要翻译: 当形成其中必须提供不同横向尺寸的通孔的复杂金属化系统时,可以应用分割图案化顺序。 为此目的,光刻工艺可以被专门设计用于临界通孔,并且随后的第二图案化工艺可用于形成增加的横向尺寸的通孔,而临界通孔被掩蔽。 以这种方式,可以为每个图案化序列建立优良的工艺条件。

    Test structure for OPC-related shorts between lines in a semiconductor device
    60.
    发明授权
    Test structure for OPC-related shorts between lines in a semiconductor device 有权
    半导体器件中线路间OPC相关短路的测试结构

    公开(公告)号:US07800106B2

    公开(公告)日:2010-09-21

    申请号:US11747320

    申请日:2007-05-11

    IPC分类号: H01L23/58 H01L29/10

    摘要: OPC results may be efficiently evaluated on the basis of a test structure containing a plurality of line features with opposing end portions. Thus, for different line parameters, the effect of OPC may be determined for a given critical tip-to-tip distance by determining the leakage behavior of the test assemblies, each having different design parameter values for line width and lateral distance between adjacent lines.

    摘要翻译: 可以基于包含具有相对端部的多个线特征的测试结构来有效地评估OPC结果。 因此,对于不同的线路参数,可以通过确定测试组件的泄漏行为来确定给定的临界尖端到尖端距离的OPC的效果,每个测试组件对于线宽和相邻线之间的横向距离具有不同的设计参数值。