公开(公告)号：US10790376B2

公开(公告)日：2020-09-29

申请号：US16105102

申请日：2018-08-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Chanro Park ,  Julien Frougier ,  Kangguo Cheng ,  Andre P. Labonte

IPC: H01L21/00 ,  H01L29/66 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/45 ,  H01L21/768 ,  H01L27/088 ,  H01L21/027 ,  H01L21/311 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L29/423 ,  H01L29/51 ,  H01L29/49 ,  H01L21/3105 ,  H01L21/3213

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to contact structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers; contacts connecting to at least one gate structure of the plurality of gate structures; and at least one metallization feature connecting to the source and drain regions and extending over the sidewall spacers.

公开(公告)号：US10770566B2

公开(公告)日：2020-09-08

申请号：US16594276

申请日：2019-10-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ruilong Xie ,  Chanro Park ,  Kangguo Cheng

IPC: H01L29/66 ,  H01L21/764 ,  H01L21/768 ,  H01L29/417 ,  H01L29/423

Abstract: A device is disclosed that includes an active layer, a gate structure positioned above a channel region of the active layer and a first sidewall spacer positioned adjacent the gate structure. The device also includes a gate cap layer positioned above the gate structure and an upper spacer that contacts sidewall surfaces of the gate cap layer, a portion of an upper surface of the gate structure and an inner surface of the first sidewall spacer.

公开(公告)号：US20200272880A1

公开(公告)日：2020-08-27

申请号：US16283887

申请日：2019-02-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Edward J. Nowak ,  Siva P. Adusumilli ,  Ruilong Xie ,  Julien Frougier

IPC: G06N3/04 ,  H01L27/24 ,  H01L29/872 ,  H01L45/00

Abstract: Embodiments of the present disclosure provide a neuromorphic circuit structure including: a first vertically-extending neural node configured to generate an output signal based on at least one input to the first vertically-extending neural node; an interconnect stack adjacent the vertically-extending neural node, the interconnect stack including a first conducting line coupled to the first vertically-extending neural node and configured to receive the output signal, a second conducting line vertically separated from the first conducting line, and a memory via vertically coupling the first conducting line to the second conducting line; and a second vertically-extending neural node adjacent the interconnect stack, and coupled to the second conducting line for receiving the output signal from the first vertically-extending neural node.

公开(公告)号：US10665669B1

公开(公告)日：2020-05-26

申请号：US16285657

申请日：2019-02-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Julien Frougier

IPC: H01L29/06 ,  H01L21/308 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L27/02 ,  H01L27/088 ,  H01L27/105

Abstract: An IC structure according to the disclosure includes an insulative structure overlying a substrate and set of STIs. The insulative structure includes an isolation layer contacting an upper surface of the substrate, and a diffusion break region integral with and extending from the isolation layer, wherein the diffusion break region horizontally separates a pair of upper surfaces of the isolation layer. A pair of active semiconductor layers, each positioned on a respective one of the pair of upper surfaces of the isolation layer, are adjacent opposing sidewalls of the diffusion break region. The isolation layer electrically separates the pair of active semiconductor layers from the substrate, and the diffusion break region electrically separates the pair of active semiconductor layers from each other.

公开(公告)号：US10608082B2

公开(公告)日：2020-03-31

申请号：US15994402

申请日：2018-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Julien Frougier ,  Ruilong Xie

IPC: H01L29/06 ,  H01L29/423 ,  H01L21/8234 ,  H01L29/10 ,  H01L29/08

Abstract: Structures for a field-effect transistor and methods of forming structures for a field-effect transistor. A semiconductor fin having a channel region, a nanowire arranged over the channel region of the semiconductor fin, a source/drain region connected with the channel region of the semiconductor fin and the nanowire, and a gate structure that overlaps with the channel region of the semiconductor fin and the nanowire. The nanowire has a first gate length, and the channel region of the semiconductor fin has a second gate length that is greater than the first gate length.

公开(公告)号：US10559656B2

公开(公告)日：2020-02-11

申请号：US15968968

申请日：2018-05-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Emilie M. S. Bourjot ,  Julien Frougier ,  Yi Qi ,  Ruilong Xie ,  Hui Zang ,  Hsien-Ching Lo ,  Zhenyu Hu

IPC: H01L29/06 ,  H01L29/417 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/285

Abstract: Described herein are nanosheet-FET structures having a wrap-all-around contact where the contact wraps entirely around the S/D epitaxy structure, thereby increasing contact area and ultimately allowing for improved S/D contact resistance. Other aspects described include nanosheet-FET structures having an air gap as a bottom isolation area to reduce parasitic S/D leakage to the substrate.

公开(公告)号：US10510620B1

公开(公告)日：2019-12-17

申请号：US16047043

申请日：2018-07-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Daniel Chanemougame ,  Steven R. Soss ,  Steven J. Bentley ,  Julien Frougier ,  Ruilong Xie

IPC: H01L21/8238 ,  H01L29/423 ,  H01L29/06 ,  H01L21/762 ,  H01L21/3213 ,  H01L29/66 ,  H01L27/092 ,  H01L27/11

Abstract: A method includes forming an isolation pillar between first and second active nanostructures for adjacent FETs. A first WFM for one FET is deposited over the first active nanostructure, the pillar and the second active nanostructure. The first WFM is removed from a part of the pillar. The removing creates a discontinuity in the first WFM over the first active nano structure from the first WFM over the second active nanostructure but leaves the first WFM on sidewalls of the pillar. When the first WFM surrounding the second active nanostructure is removed, the pillar and the discontinuity in the first metal on the part of the pillar prevent the etching from reaching and removing the first WFM on the first active nanostructure. Depositing a second WFM surrounding the second active nanostructure and the isolation pillar forms part of the gate for the second FET and couples the FETs together.

公开(公告)号：US20190288117A1

公开(公告)日：2019-09-19

申请号：US15920886

申请日：2018-03-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Christopher M. Prindle ,  Nigel G. Cave

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

Abstract: The disclosure relates to gate-all-around (GAA) transistors with a spacer support, and related methods. A GAA transistor according to embodiments of the disclosure includes: at least one semiconductor channel structure extending between a source terminal and a drain terminal; a spacer support having a first portion thereof positioned underneath and a second portion thereof positioned alongside a first portion of the at least one semiconductor channel structure; and a gate metal surrounding a second portion of the at least one semiconductor channel structure between the source and drain terminals; wherein the spacer support is positioned between the gate metal and the source or drain terminal.

公开(公告)号：US20190214482A1

公开(公告)日：2019-07-11

申请号：US15865973

申请日：2018-01-09

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Julien Frougier ,  Yi Qi ,  Nigel G. Cave ,  Edward J. Nowak ,  Andreas Knorr

IPC: H01L29/66 ,  H01L29/161 ,  H01L21/02 ,  H01L29/10 ,  H01L29/06 ,  H01L21/308 ,  H01L29/78

CPC classification number: H01L29/66598 ,  H01L21/02532 ,  H01L21/3086 ,  H01L27/00 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/66818 ,  H01L2029/7858

Abstract: A semiconductor structure including a first substantially U-shaped and/or H-shaped channel is disclosed. The semiconductor structure may further include a second substantially U-shaped and/or H-shaped channel positioned above the first channel. A method of forming a substantially U-shaped and/or H-shaped channel is also disclosed. The method may include forming a fin structure on a substrate where the fin structure includes an alternating layers of sacrificial semiconductor and at least one silicon layer or region. The method may further include forming additional silicon regions vertically on sidewalls of the fin structure. The additional silicon regions may contact the silicon layer or region of the fin structure to form the substantially U-shaped and/or H-shaped channel(s). The method may further include removing the sacrificial semiconductor layers and forming a gate structure around the substantially U-shaped and/or substantially H-shaped channels.

公开(公告)号：US10332803B1

公开(公告)日：2019-06-25

申请号：US15973817

申请日：2018-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Edward J. Nowak ,  Bipul C. Paul ,  Steven R. Soss ,  Julien Frougier ,  Daniel Chanemougame ,  Lars W. Liebmann

IPC: H01L21/8238 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/092

Abstract: Various embodiments relate to gate-all-around (GAA) transistors and methods of forming such transistors. In some embodiments, a method performed on a precursor structure includes selectively removing a sacrificial nanosheet to open a vertical gap between a pair of semiconductor nanosheets; forming a first work function metal to surround the precursor nanosheet stack and fin, the first work function metal filling the vertical gap between the pair of semiconductor nano sheets; selectively removing first work function metal surrounding the fin while preserving an entirety of first work function metal surrounding the nanosheet stack; and forming a second work function metal: over a remaining portion of the first work function metal on nanosheet stack, and surrounding the fin, where first work function metal includes a different material than second work function metal.